A trench transistor cross-point DRAM cell

Richardson, W. H.; Bordelon, D.M.; Pollack, G.; Shah, A.H.; Malhi, S.D.S.; Shichijo, H.; Banerjee, S.; Elahy, M.; Womack, R.H.; Wang, C.-P.; Gallia, J.; Davis, H.E.; Chatterjee, P.K.

doi:10.1109/iedm.1985.191075

Cited by 42 publications

(3 citation statements)

References 4 publications

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“…transistor cells (TIC) [49]. These structures are similar to that of the trench structure, except that the charge storage is moved to the dielectrically isolated polysilicon inside the trench and the substrate forms the constant-potential field plate, as shown in Fig.…”

Section: A Cell Designmentioning

confidence: 97%

Cosmic and terrestrial single-event radiation effects in dynamic random access memories

Massengill

1996

IEEE Trans. Nucl. Sci.

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A review of the literature on single-event radiation effects (SEE) on MOS integrated-circuit dynamic random access memories (DRAM's) is presented. The sources of single-event (SE) radiation particles, causes of circuit informatidn loss, experimental observations of SE information upset, technological developments for error mitigation, and relationships of developmental trends to SE vulnerability are discussed.

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Section: A Cell Designmentioning

confidence: 97%

Cosmic and terrestrial single-event radiation effects in dynamic random access memories

Massengill

1996

IEEE Trans. Nucl. Sci.

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“…Examples of these structures include dynamic memory cells [l], merged BiCMOS static memory cells [2], and NMOS input and PMOS input merged bipolar/sidewall-MOS transistors (NBiMOS and PBiMOS) [3], [4]. In this paper, a concept of merging a vertical n-p-n bipolar and two sidewall NMOS transistors into an NMOS input merged bipolar/sidewall-MOS transistor with a bypass sidewall NMOS transistor structure (NBiBMOS transistor) is described.…”

Section: Introductionmentioning

confidence: 99%

An NMOS input merged bipolar/sidewall-MOS transistor with a bypass sidewall MOS transistor (NBiBMOS transistor)

Lutsky

Reif

Lee

1992

IEEE Electron Device Lett.

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A concept of merging a vertical n-p-n bipolar and two sidewall NMOS transistors into an NMOS input merged bipolar / sidewall-MOS transistor with a bypass sidewall NMOS transistor structure (NBiBMOS transistor) is described. The output current of this structure, unlike that of NBiMOS transistors, is significant even when the output voltage (VcE or VDE) is less than the turn-on voltage of the n-p-n bipolar transistor (VBE = -0.8 V). This structure, when used in BiCMOS logic gates, will allow the output voltage to swing all the way to 0.0 V rather than to 0.8 V. The feasibility of this concept was demonstrated by fabricating and dc characterizing the NBiBMOS transistor structures which occupy -1.2 times the area of a single n-p-n bipolar transistor. The area occupied by the NBiB-MOS transistor which merges three transistors is the same as that of the previously described NBiMOS transistor which merges two transistors. In addition, the NBiBMOS transistor has a higher drive capability than that of a structure consisting of an NBiMOS and a separate bypass transistor because the body-source junction of the bypass NMOS transistor is forward biased.

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“…The VMOS transistor [1] with 1 im vertical channel was among the first studies in this field, and a number ofproposals [2,3,4,5,6,7,9Jhave since been made for sub-micron vertical MOS transistors. Photolithography technologies currently used for patterning submicron channel length MOS transistors are quickly approaching practical and fundamental limits.…”

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confidence: 99%

Sub-0.1-μm vertical MOS transistor

Mori¹

1999

SPIE Proceedings

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A sub 0.1 microns channel length vertical MOS transistor was developed for processing with equipment typically utilized for older generation devices. One of the important advantages of vertical MOS transistor technology is that the channel length scaling is not limited by the minimum lithographic resolution. The vertical Ldd processing was also developed to improve the short channel effects. The transistor with channel length below 0. 1 tm has normal characteristics at room temperature, a >6V Bvdss, and a Iransconductance with value as high as in the conventional planar transistor of the same channel length.Short channel length MOS transistors are always desired for ULSI devices with higher packing density, and much

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A trench transistor cross-point DRAM cell

Cited by 42 publications

References 4 publications

Cosmic and terrestrial single-event radiation effects in dynamic random access memories

Cosmic and terrestrial single-event radiation effects in dynamic random access memories

An NMOS input merged bipolar/sidewall-MOS transistor with a bypass sidewall MOS transistor (NBiBMOS transistor)

Sub-0.1-μm vertical MOS transistor

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