Application-specific integrated circuits (ASICs) are commonly used to efficiently process the signals from sensors and detectors in space. Wire bonding is a space-qualified technique of making interconnections between ASICs and their substrate packaging board for power, control, and readout of the ASICs. Wire bonding is nearly ubiquitous in modern space programs, but their exposed wires can be prone to damage during assembly and subject to electric interference during operations. Additional space around the ASICs needed for wire bonding also impedes efficient packaging of large arrays of detectors. Here, we introduce the through silicon vias (TSV) technology that replaces wire bonds and eliminates their shortcomings. We have successfully demonstrated the feasibility of implementing TSVs to existing ASIC wafers (a.k.a. a via-last process) developed for processing the x-ray signals from the x-ray imaging CdZnTe detectors on the Nuclear Spectroscopic Telescope Array small explorer telescope mission that was launched in 2012. While TSVs are common in the semiconductor industry, this is the first (to our knowledge) successful application for astrophysics imaging instrumentation. We expect that the TSV technology will simplify the detector assembly and thus will enable significant cost and schedule savings in assembly of large area CdZnTe detectors.

This paper will describe the use of through-silicon vias (TSVs) in a readout application-specific integrated circuit (ASIC) chip to replace wire bonds in the assembly of cadmium zinc telluride (CZT) X-ray detector arrays for space telescope applications. The TSV packaging approach includes solder bump connections from the back of the ASIC to the underlying board. This approach will greatly reduce the spacing between adjacent detectors in an array, eliminate potential damage to wires during assembly, and avoid any interference, which the wires can pick up during operation.We report a TSV-last integration process for the mixed signal ASIC chip used to read signals from the CZT detectors. The TSVs were integrated into existing ASIC wafers without any required redesign, and formed as blind vias from the frontside of the ASIC in metal-free areas adjacent to the wire bond pads. The TSVs were then connected to the bond pads using a routing metal layer. The wafers were bonded to temporary carriers and thinned from the backside, revealing the TSVs. After forming the redistribution lines (RDL) and under bump metallization (UBM), the wafers were released from the carriers and solder bumps were attached for subsequent assembly processes.In the sections that follow, we will review the details of the ASIC wafer post-processing, including TSV fabrication, wafer thinning, frontside and backside metallization layers, and solder bumping. We will report electrical testing of TSV daisy chains and isolation test structures. Also, results of ASIC functionality testing, performed before and after TSV insertion, will be discussed.

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