TSV-Last Integration to Replace ASIC Wire Bonds in the Assembly of X-Ray Detector Arrays

Abstract

This paper will describe the use of through-silicon vias (TSVs) in a readout application-specific integrated circuit (ASIC) chip to replace wire bonds in the assembly of cadmium zinc telluride (CZT) X-ray detector arrays for space telescope applications. The TSV packaging approach includes solder bump connections from the back of the ASIC to the underlying board. This approach will greatly reduce the spacing between adjacent detectors in an array, eliminate potential damage to wires during assembly, and avoid any interference, which the wires can pick up during operation.We report a TSV-last integration process for the mixed signal ASIC chip used to read signals from the CZT detectors. The TSVs were integrated into existing ASIC wafers without any required redesign, and formed as blind vias from the frontside of the ASIC in metal-free areas adjacent to the wire bond pads. The TSVs were then connected to the bond pads using a routing metal layer. The wafers were bonded to temporary carriers and thinned from the backside, revealing the TSVs. After forming the redistribution lines (RDL) and under bump metallization (UBM), the wafers were released from the carriers and solder bumps were attached for subsequent assembly processes.In the sections that follow, we will review the details of the ASIC wafer post-processing, including TSV fabrication, wafer thinning, frontside and backside metallization layers, and solder bumping. We will report electrical testing of TSV daisy chains and isolation test structures. Also, results of ASIC functionality testing, performed before and after TSV insertion, will be discussed.

Tuning of nuclear spectroscopic telescope array application specific integrated circuits to improve low energy threshold of future hard x-ray imaging detectors

“…This improvement in resolution will ultimately be affected by the optimally chosen 4Vsel register value. Figure 10 includes resolution data from the pixel (16,16) data presented in Fig. 7(a) for the most optimal 4Vsel value of 59, as well as values with strong positive and negative voltage ramping (4Vsel of 0 and 75, respectively).…”

“…14 readout lines routed through the NuASIC's silicon substrate to its back surface through a via-last process. 16 This TSV-enabled design will ultimately improve instrument integration by replacing the previously required 87 individual wire bonds per detector with a simpler and more robust flip-chip bonding process. To probe a "bare" unattached TSV-NuASIC, we have designed and built an ASIC test stand (ATS) for control and data readout that contacts the device using an array of micropogo probes.…”

Testing station for fast screening of through silicon via-enabled application-specific integrated circuits for hard x-ray imaging detectors

“…Challenges with implementing the backside TSVs successfully 7 led to the exploration of a frontside through TSV design with Micross Advanced Interconnect Technology. 13 In this process, three 20 μm diameter TSVs are etched adjacent to each of the wire bond pads, then revealed on the backside of the NuASICs through a polishing and etching process before backside traces are deposited. The first run of the frontside TSV NuASICs tested with the ATS produced a functioning device yield of ∼30%.…”

Design, Manufacture and Assembly of 3D Integrated Optical Transceiver Module Based on an Active Photonic Interposer

“…Some methods can also be adopted in the packaging substrate to facilitate fiber coupling, such as substrate hollowing out. For active silicon interposer, there are three main TSV fabrication processes, which are "TSV-first" [21], "TSV-middle" [22] and "TSV-last" [23], as shown in Figure 2.…”

“…For active silicon interposer, there are three main TSV fabrication processes, which are "TSV-first" [21], "TSV-middle" [22] and "TSV-last" [23], as shown in Figure 2. In this paper, two dummy EIC (electrical integrated circuit) chips are designed for 3D assembly.…”