A true single-phase 8-bit adiabatic multiplier

Kim, Suhwan; Ziesler, C.H.; Papaefthymiou, Marios C.

doi:10.1145/378239.379061

Cited by 22 publications

(9 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Our chip was first presented in [9], while a more detailed description and comparative evaluation followed in [10]. In this section, we summarize and highlight key aspects of the design.…”

Section: Power-clock Generatormentioning

confidence: 99%

“…The first chip is a 130MHz dynamic multiplier designed in a source-coupled adiabatic dynamic logic [9,10] and fabricated in 0.5 m bulk silicon. The second chip is a 300MHz resonant-clocked ASIC for the Discrete Wavelet Transform that has been synthesized using industry-standard tools [25] and has been fabricated in a 0.25 m bulk silicon process.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Fast, efficient, recovering, and irreversible

Sathe

Chueh

Kim

et al. 2005

Proceedings of the 2nd Conference on Computing Frontiers

Self Cite

View full text Add to dashboard Cite

Recent advances in CMOS VLSI design have taken us to real working chips that rely on controlled charge recovery to operate at substantially lower power dissipation levels than their conventional counterparts. In this paper, we present two such chips that were designed in our research group and highlight some of the promising charge-recovery techniques in practice. Although their origins can be traced back to the early adiabatic circuits, these techniques approach energy recycling from a more practical angle, shedding reversibility to achieve operating frequencies in excess of 1GHz with relatively low overheads.

show abstract

“…Our chip was first presented in [9], while a more detailed description and comparative evaluation followed in [10]. In this section, we summarize and highlight key aspects of the design.…”

Section: Power-clock Generatormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Fast, efficient, recovering, and irreversible

Sathe

Chueh

Kim

et al. 2005

Proceedings of the 2nd Conference on Computing Frontiers

Self Cite

View full text Add to dashboard Cite

show abstract

“…Because the adiabatic loads driven by the oscillator outputs are different and time variable (Kim et al, 2001), the circuit cannot be completely balanced with external capacitances, therefore a phase error up to 5% may occur in the output waveforms. If outputs are used as internal control signals, i.e.…”

Section: Overview Of Adiabatic Oscillatorsmentioning

confidence: 99%

Resonant 90 degree shifter generator for 4-phase trapezoidal adiabatic logic

et al. 2003

View full text Add to dashboard Cite

Abstract. Many adiabatic logic families make use of multi phase trapezoidal or sinusoidal power clocks to recover the energy stored in the load capacitances. A key aspect for the evaluation of the performance of adiabatic logic is then the study of a system that includes the power clock generator. A four-phase trapezoidal power clock generator, according to the requirements of the most promising architectures, namely the ECRL and PFAL, has been designed and simulated. The proposed circuit, realized with a double-well 0.25 µm CMOS technology and external inductors, is a resonant generator designed to oscillate at a frequency of 7 MHz, which is within the optimum frequency range for adiabatic circuits realized with this CMOS technology. The generator has been simulated with the equivalent load of fifty 1-bit adders and the operating behavior of a 4-bit adder has been evaluated. The key aspects of a generator for adiabatic logic are its power consumption and the phase relationships between its output signals. The proposed generator has a conversion efficiency higher than 80%, and it is robust with respect to variations of technology parameters. The four power supplies exhibit the correct relationship of phase also in the presence of no equally distributed loads.

show abstract

“…To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. ISLPED'05, August 8-10, 2005 [8,9], and the inefficient resolution of complementary outputs of dual-rail gates during evaluation [2,4].…”

Section: Introductionmentioning

confidence: 99%

A GHz-class charge recovery logic

Sathe

Papaefthymiou

Ziesler³

2005

Proceedings of the 2005 International Symposium on Low Power Electronics and Design - ISLPED '05

Self Cite

View full text Add to dashboard Cite

This paper describes Boost Logic, a logic family which relies on voltage scaling, gate overdrive, and energy recovery, to achieve high energy efficiency at GHz frequencies.The key feature of our design is an energy recovering "boost" stage that provides a high gate overdrive to an aggressively voltage-scaled logic at nearthreshold supply voltage. We have evaluated Boost Logic through post-layout simulation of an 8-bit carry-save multiplier in a ¢ ¡ ¤ £ ¦ ¥ § m CMOS process with © =340mV. At 1.6GHz and 1.3V supply voltage, the Boost multiplier dissipates 8.11pJ per computation, yielding 68% energy savings over its pipelined, voltage-scaled static CMOS counterpart. Using low © devices, the Boost Logic multiplier has been verified to operate at 2GHz with a 1.25V voltage supply and 8.50pJ energy dissipation per cycle.

show abstract

A true single-phase 8-bit adiabatic multiplier

Cited by 22 publications

References 12 publications

Fast, efficient, recovering, and irreversible

Fast, efficient, recovering, and irreversible

Resonant 90 degree shifter generator for 4-phase trapezoidal adiabatic logic

A GHz-class charge recovery logic

Contact Info

Product

Resources

About