A two-residue architecture for multistage ADCs

Abstract

A major limitation of multistage or pipeline ADC architectures is the need for a gain element between stages when the overall resolution exceeds about 9b. This gain element amplifies the residue of the first-stage conversion to a level that can be digitized by subsequent stages. The accuracy and settling requirements for this interstage amplifier dictates large gainbandwidth and leads to large power consumption. The architecture described here uses two residue signais to reduce amplifier requirements.

BIST Method for Die-Level Process Parameter Variation Monitoring in Analog/Mixed-Signal Integrated Circuits

“…Namely, we see mean value extracted from Figure 9, the weighted sigmas of each measurement and their relative position to the actual test limits. We regard the device as probably faulty if it falls outside the limits given by equation (9). Typical circuit design is based on worstcase process variability conditions to ensure circuit functionality in various process corners.…”

“…A gain error in the residue amplifier scales the total range of residue signal (signal as a result of the subtraction of the input signal and the DAC signal) and causes an error in the analog input to the next stage when applied to any nonzero residue, which will result in a residue signal not fitting in the fine ADC range. To elevate this problem, two residue amplifiers [9] have been employed. According to coarse quantization decision, a first and a second residue amplifier pass the difference between the analog signal and the closest and the second closest quantization level, respectively.…”

An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers

“…Alternatively, the interpolation technique [18], [20] can be applied in a pipeline fashion [19], [21], [22]; thus, the gain accuracy requirement of the residue amplifiers shifts from absolute to relative gain accuracy between a pair of residue amplifiers. Due to the relaxed gain requirement, open-loop amplifiers with simple topologies can be employed.…”

Digital Adaptive Calibration of Multi-Step Analog to Digital Converters

“…If the error in the analog input to the fine ADC stage is more than one part in 2 r (where r is the resolution remaining after the residue amplifier gain error), it will result in a conversion error, which can lead to nonmonotonicity or missing codes, that is not removed by digital correction. In our design, the implemented dual-residue signal processing 28 as illustrated in Figure 4(b) spreads the errors of the residue amplifiers over the whole mid and fine range, which results in an improved linearity. According to quantization decision of the previous stage, a first and a second residue amplifier pass the difference between the analog signal and the closest and the second closest quantization level, respectively.…”