A unified modulo scheduling and register allocation technique for clustered processors

Abstract

This work presents a modulo scheduling framework for clustered ILP processors that integrates the cluster assignment, instruction scheduling and register allocation steps in a single phase. This unified approach is more effective than traditional approaches based on sequentially performing some (or all) of the three steps, since it allows optimizing the global code generation problem instead of searching for optimal solutions to each individual step. Besides, it avoids the iterative nature of traditional approaches, which require repeated applications of the three steps until a valid solution is found. The proposed framework includes a mechanism to insert spill code on-the-fly and heuristics to evaluate the quality of partial schedules considering simultaneously inter-cluster communications, memory pressure and register pressure. Transformations that allow trading pressure on a type of resource for another resource are also included. We show that the proposed technique outperforms previously proposed techniques. For instance, the average speed-up for the SPECfp95 is 36% for a 4-cluster configuration.

AGAMOS: A Graph-Based Approach to Modulo Scheduling for Clustered Microarchitectures

“…Both tasks are carried out at the same time, generating spill code on the fly when needed. The approach is based on the URACAM modulo scheduling framework for clustered VLIW architectures [14].…”

“…More recent approaches [14], [37] perform cluster assignment, instruction scheduling and register allocation in a single step. These algorithms are the state-of-the-art and we use them as our baseline.…”

A software-hardware hybrid steering mechanism for clustered microarchitectures

“…All previous work can be classified according to their compilation scopes. One important category is the code generation for loops [1,2,10,20,25] by means of modulo scheduling techniques [9,23]. Another category schedules instructions for more general program structures including cyclic and acyclic control flow graphs [6,8,12,13,16,17,21].…”

Heterogeneous Clustered VLIW Microarchitectures

“…On the other hand, several modulo scheduling approaches targeting clustered VLIW architectures have been proposed [24][11] [29] [7][2] [3]. All these works have targeted homogeneous microarchitectures.…”