A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques

Abstract

Scan chains are popularly used as the channels for silicon testing and debugging. However, they have also been identified as one of the culprits of silicon failure more recently. To cope with this problem, several scan chain diagnosis approaches have been proposed in the past. The existing methods, however, suffer from one common drawback-that is, they rely on fault models and matching heuristics to locate the faults. Such a paradigm may run into difficulty when the fault under diagnosis does not match the fault model exactly, for example, when there is a bridging between a flip-flop and a logic cell, or the fault is temporal and only manifests itself intermittently. In light of this, we propose in this article a more versatile model-free paradigm for locating the faulty flip-flops in a scan chain, incorporating a number of signal processing techniques, such as filtering and edge detection. These techniques performed on the test responses of the failing chip under diagnosis directly can effectively reveal the fault location(s) in a scan chain. As compared to the previous works, our approach is better capable of handling intermittent faults and bridging faults, even under nonideal conditions, for example, when the core logic is also faulty. Experimental results on several real designs indicate that this approach can indeed catch some nasty faults that previous methods could not catch.

Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic Defects

“…bit b1 passes through path P3 consisting of scan cells (1,3,6,9,10) and then is observed as r1. If r1 differs from b1, we can conclude that the faulty scan cell must be one of the five cells in P3.…”

“…After the flush test, a SA-fault can be narrowed down to two symmetric nodes (one in the top part and the other in the bottom part) or one node (in the middle part); a missing-edge fault can be narrowed down to some symmetric parts (for example part (2,4,5,8) or (3,6,7,9) in Fig.1); a missing-clock fault can be narrowed down to one candidate, but we cannot distinguish it from the SA-fault in the same position. Therefore, we first give the scheme to distinguish two SA-faults in the symmetric nodes and the missing-clock fault in the top part.…”

“…1 as an example, if nodes (2,4,5,8) or (3,6,7,9) are inaccessible, only the first 6 bits during the unloading process for a pattern are captured response bits, while the other four bits are error bits. Based on the values of the 6 observed response bits, we can determine which part (nodes (2,4,5,8) or (3,6,7,9)) is inaccessible. Therefore, for a DTS with inaccessible candidate parts, P1 and P2, we first calculate the expected response of P1 and P2 for each pattern.…”

“…Many early scan chain diagnosis methods make the unrealistic assumption that the system logic is fault-free [14]. The diagnosis process is considerably more challenging for a compound fault model in which system logic faults can co-occur with scan chain faults and can corrupt the test results obtained in the absence of system logic faults [2,3,6,16]. Prior studies that allow compound faults in scan chain diagnosis, however, are limited to solutions that solve specific cases or can tolerate only a small number of logic defects for perfect diagnosis.…”