A VLSI Implementation of a Generic Systolic Synaptic Building Block for Neural Networks

Analysis of Fault Tolerance in Artificial Neural Networks

“…A second class of digital implementations considers simulation of the neural network by distributing the computation in the whole array instead of associating neurons to array nodes [29]. No mapping (possibly through time multiplexing) of synapses onto interconnection links can be identified: a row of the rectangular array is dedicated to simulation of an individual neuron (see Fig.…”

Time redundancy for error detecting neural networks

“…is dependent on the function itself. In the general case, a self-dual circuit can be designed as shown in [15]. This may require a circuit whose complexity is more than twice the nominal one since one of the circuits implements the nominal function, another implements the dual function, and a multiplexer selects the output.…”