A wide-band 10-b 20 Ms/s pipelined ADC using current-mode signals

Real, P.; Robertson, David; Mangelsdorf, Chris; Tewksbury, T.

doi:10.1109/4.90063

Cited by 37 publications

(7 citation statements)

References 8 publications

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“…To achieve a positive CINJ, the switch is a PMOS. Similar to (8) and (9), the CINJ current offset can be derived (16) where (17) where is the threshold voltage of PMOS. The FIMP current offset is similarly derived as (7) (18) where is the transistor parameter for M2.…”

Section: B S I Mdacmentioning

confidence: 99%

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Modeling, Quantitative Analysis, and Design of Switched-Current Pipeline A/D Converters

Yuan

2009

IEEE Trans. Circuits Syst. I

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Switched-current (SI) analog-to-digital converters (ADCs) are desirable for biomedical applications. Until now, SI ADCs are lacking effective and systematic computer-aided analysis and design (CAD) tools, particularly for noise. In this paper, models for different SI multiplying-digital-to-analog-converter (MDAC) designs are analytically derived, with the inclusion of distortion and noise. The models can be further programmed into an equation-based SI analog CAD tool. In this paper, the equation-based models (EBMs) are used to quantitatively analyze SI MDACs. Simulation results show that noise significantly limit the performance of SI MDACs. Optimal performance boundaries are derived for single-ended and fully differential SI MDACs. The boundaries from EBMs are consistent with the published SI circuit measurements. A methodology is formulated to design efficient SI MDACs. The EBM and the design methodology are further verified by designs of two sample SI MDACs in an AMS 0.35-m CMOS process with SPICE simulation. Results from the EBM match those from real circuit models well, except for the noise of SI MDACs with feedback, in which case, the design margin should be added to the target performance. For low-/medium-resolution ( 12 bit) applications, a pipeline ADC with a simple SI MDAC is the most efficient. Nonetheless, single-ended SI ADCs are susceptible to source noise. For high-resolution applications, only fully differential SI pipeline ADCs can be selected.Index Terms-Analog computer-aided analysis and design (CAD), distortion, equation based, multiplying digital-to-analog converter (MDAC), noise, pipeline analog-to-digital converters (ADCs), simulation based, switched capacitor, switched current.

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Section: B S I Mdacmentioning

confidence: 99%

“…1 shows the measurements of major SI pipeline/cyclic ADCs, the sample/hold stages reported so far [10]- [20] of which [10]- [15] are single-ended designs. In [16] and [17], differential pipeline ADCs are discussed. In [18]- [20], fully differential designs are presented.…”

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confidence: 99%

Modeling, Quantitative Analysis, and Design of Switched-Current Pipeline A/D Converters

Yuan

2009

IEEE Trans. Circuits Syst. I

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“…Although VM clocking is widely used due to the compatibility with standard VM logic networks, CM clocking can play an important role in low-power systems. CM signaling offers many potential advantages such as higher operating speed [1], low voltage operation [2], and ease of processing [3] compared to VM techniques.…”

Section: Introductionmentioning

confidence: 99%

Differential current-mode clock distribution

Islam

Fahmy

Lin

et al. 2015

2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)

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Abstract-In this paper, we present a differential current-mode pulsed flip-flop (DCMPFF) for low-power clock distribution using a representative 45nm CMOS technology. Experimental results show that the DCMPFF has 47% faster clock-to-output (CLK-Q) delay than a traditional voltage-mode (VM) pulsed flip-flop. When the DCMPFF is integrated with a differential currentmode clock distribution, the differential technique saves 62% and 17% power compared to a conventional VM and a previous current-mode (CM) clock network, respectively.

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“…As a result, mixed-mode processes weight the analog requirements more heavily than digital ones. This was true of linear-compatible 12L, and for nearly a decade with the dominance of CMOS logic, RiC-MOS processes have been the choice of designers who work in both analog and digital realms [1,2].…”

Section: Introductionmentioning

confidence: 99%

BiCMOS process design for mixed-signal applications

Scharf

[Proceedings] 1992 IEEE International Symposium on Circuits and Systems

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A wide-band 10-b 20 Ms/s pipelined ADC using current-mode signals

Cited by 37 publications

References 8 publications

Modeling, Quantitative Analysis, and Design of Switched-Current Pipeline A/D Converters

Modeling, Quantitative Analysis, and Design of Switched-Current Pipeline A/D Converters

Differential current-mode clock distribution

BiCMOS process design for mixed-signal applications

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