A wide common-mode fully-adaptive multi-standard 12.5Gb/s backplane transceiver in 28nm CMOS

Savoj, Jafar; Hsieh, Kenny; Upadhyaya, Parag; An, Fu-Tai; Bekele, Ade; Chen, Stanley; Jiang, Xuewen; Lai, Kang Wei; Poon, Chi Fung; Sewani, Aman; Turker, Didem; Venna, Karthik; Wu, Daniel; Xu, Bruce; Alon, Elad; Chang, Ken

doi:10.1109/vlsic.2012.6243811

Cited by 21 publications

(2 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The overall architecture of the proposed transceiver is shown in Figure 1. A 3-tap FFE is introduced in the transmitter to pre-emphasize the input signal, and an analog front end with three-stage CTLE and VGA, CDR and 4-tap DFE are involved in the half-rate receiver [8][9][10] [11] [12]. For DFE design simplification, the architecture of direct feedback is adopted, and the semi-interleaved feedback method is proposed to further improve the feedback speed under the condition of satisfying key timing constraints [13].…”

Section: Figure 1 Overall Block Diagram Of the Transceivermentioning

confidence: 99%

A PAM4 transceiver design scheme with threshold adaptive and tap adaptive

Liu

Wen

et al. 2023

Preprint

View full text Add to dashboard Cite

To meet the demand of low bit error rate (BER) and high bandwidth for high-speed links, a reliable 112Gb/s four-level pulse amplitude modulation (PAM4) transceiver design scheme with adaptive threshold voltage and adaptive decision feedback equalizer (DFE) is proposed in this paper. In this scheme, three continuous time linear equalizers (CTLE) at the front end of receiver are used to compensate the high-frequency, mid-frequency and low-frequency signals respectively, and the variable gain amplifier (VGA) and saturation amplifier (SatAmp) are used to scale the signal amplitude. In addition to the three data samplers, four auxiliary samplers are also used for threshold adaptation. The sign-sign least mean squares algorithm uses the offset between the data sampler and the auxiliary sampler at the receiver side to drive the auxiliary reference voltage to converge to the signal constellation level, thus ensuring that the eye diagram of the PAM4 received signal has equal spacing and a constant signal-noise ratio (SNR) for the three eyes in the vertical direction. In addition, the adaptive DFE for PAM4 signaling allows the transceiver to better adapt to the channel and thus achieve better equalizer performance. The simulation results show that the PAM4 transceiver design can compensate up to 25dB of channel loss with an average eye height of 59.6 mv and an average eye width of 0.27 UI at a bit error rate of 10− 12 under the condition of 3 tap Feedforward equalizer (FFE) transmitter.

show abstract

Section: Figure 1 Overall Block Diagram Of the Transceivermentioning

confidence: 99%

A PAM4 transceiver design scheme with threshold adaptive and tap adaptive

Liu

Wen

et al. 2023

Preprint

View full text Add to dashboard Cite

show abstract

“…Therefore, it is of great significance to develop a multiple standards wireline transceiver to meet the urgent needs of real-time, flexible interconnection, and high-speed data exchange among devices with different protocols. Most of the research on multiple standards has been reported in which these designs targeted at field-programmable gate arrays (FPGAs) application [1][2][3][4][5][6]. And an FPGA transceiver support many protocols and must have fine-grain programmability.…”

Section: Introductionmentioning

confidence: 99%

An 11.05 mW/Gbps Quad-Channel 1.25-10.3125 Gbps Serial Transceiver With a 2-Tap Adaptive DFE and a 3-Tap Transmit FFE in 40 nm CMOS

Chen

Wang

et al. 2021

IEEE Access

View full text Add to dashboard Cite

This paper presents a quad-channel 1.25-10.3125 Gbps wireline transceiver implemented in 40 nm CMOS technology. The transmitter consists of a bit width adjustment, a 40:2 multiplexer, a 2:1multiplexer, and a current-mode logic driver with a 3-tap feedforward equalizer. The receiver has a twostage continuous-time linear equalizer, a 2-tap half-rate fully adaptive decision-feedback equalizer, a phase interpolation-based digital clock and data recovery (CDR) followed by a 2:40 demultiplexer, a bit width adaption. The transceiver also supports AC/DC coupling, CDR locking detection, PLL locking detection, loss of signal detection, automatic termination impedance calibration. A ring VCO-based PLL is designed in each lane to save power consumption, and a dual-core LC VCO-based PLL is implemented in each bank to generate a low jitter clock signal. At 10.3125 Gbps, the transceiver can equalize 28 dB Nyquist loss at a bit error rate of 10 −12 , and it consumes 114 mW with a 1.1 V supply. This work presents a high power efficiency of 11.05 mW/Gbps, and the transceiver is suitable for multi-standard applications due to its flexibility and power efficiency.INDEX TERMS Transceiver, feedforward equalizer, continuous-time linear equalizer (CTLE), adaptive decision-feedback equalizer (DFE), clock and data recovery (CDR).

show abstract