Accelerated two-level carry-skip adders-a type of very fast adders

Kantabutra, Vitit

doi:10.1109/12.247841

Cited by 21 publications

(7 citation statements)

References 8 publications

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“…The techniques presented in [19]- [24] make use of VSSs to minimize the delay of adders based on a singlelevel carry skip logic. In [25], some methods to increase the speed of the multilevel CSKAs are proposed. The techniques, however, cause area and power increase considerably and less regular layout.…”

Section: A Modifying Cskas For Improving Speedmentioning

confidence: 99%

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

Bahadori

Kamal

Afzali-Kusha

et al. 2016

IEEE Trans. VLSI Syst.

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In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, which lowers the power consumption without considerably impacting the speed, is presented. This extension utilizes a modified parallel structure for increasing the slack time, and hence, enabling further voltage reduction. The proposed structures are assessed by comparing their speed, power, and energy parameters with those of other adders using a 45-nm static CMOS technology for a wide range of supply voltages. The results that are obtained using HSPICE simulations reveal, on average, 44% and 38% improvements in the delay and energy, respectively, compared with those of the Conv-CSKA. In addition, the power-delay product was the lowest among the structures considered in this paper, while its energy-delay product was almost the same as that of the Kogge-Stone parallel prefix adder with considerably smaller area and power consumption. Simulations on the proposed hybrid variable latency CSKA reveal reduction in the power consumption compared with the latest works in this field while having a reasonably high speed.Index Terms-Carry skip adder (CSKA), energy efficient, high performance, hybrid variable latency adders, voltage scaling.

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Section: A Modifying Cskas For Improving Speedmentioning

confidence: 99%

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

Bahadori

Kamal

Afzali-Kusha

et al. 2016

IEEE Trans. VLSI Syst.

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“…Since the carry generated by the previous block, C 10, takes 4 levels of logic, the block P and G logic in this block has one more logic level to balance the carry chain inputs. Applying the factor of three discussed in the previous section, the total number of bits in this block is three times as large as the previous blocks, which gives a block size of 18 bits.…”

Section: -Bit Blockmentioning

confidence: 99%

“…Several studies have been performed to reduce the delay of carry-skip adders [6][7][8][9][10]. Techniques presented in [6,7] select variable block sizes to minimize the delay of adders that use a single level of carry skip logic.…”

Section: Introductionmentioning

confidence: 99%

“…Techniques presented in [6,7] select variable block sizes to minimize the delay of adders that use a single level of carry skip logic. Techniques presented in [8][9][10] allow multiple levels of skip logic, which further reduces delay at the cost of an increase in area and less regular layout. Although the techniques presented in [6][7][8][9][10] reduce the delay of carry skip adders, they did not take into account further delay optimizations that can achieved by complementary carry generation and the use of carry look-ahead techniques within the blocks.…”

Section: Introductionmentioning

confidence: 99%

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A static low-power, high-performance 32-bit carry skip adder

Chirca

Schulte

Glossner

et al. 2004

Euromicro Symposium on Digital System Design, 2004. DSD 2004.

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“…The fan-in to the carry-skip logic increases linearly towards the middle of the adder. A two-level carry-skip adder is presented in [9], where the whole adder stage is divided into a number of sections, each consisting of a number of RCA blocks of linearly increasing length. These adders reduce the delay at the cost of an increase in area and less regular layout.…”

Section: Vlsi Designmentioning

confidence: 99%

Delay Efficient 32‐Bit Carry‐Skip Adder

Lin

Radhakrishnan

2008

VLSI Design

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The design of a 32-bit carry-skip adder to achieve minimum delay is presented in this paper. A fast carry look-ahead logic using group generate and group propagate functions is used to speed up the performance of multiple stages of ripple carry adders. The group generate and group propagate functions are generated in parallel with the carry generation for each block. The optimum block sizes are decided by considering the critical path into account. The new architecture delivers the sum and carry outputs in lesser unit delays than existing carry-skip adders. The adder is implemented in 0.25 μm CMOS technology at 3.3 V. The critical delay for the proposed adder is 3.4 nanoseconds. The simulation results show that the proposed adder is 18% faster than the current fastest carry-skip adder.

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Accelerated two-level carry-skip adders-a type of very fast adders

Cited by 21 publications

References 8 publications

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

A static low-power, high-performance 32-bit carry skip adder

Delay Efficient 32‐Bit Carry‐Skip Adder

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