Accelerating Multiprocessor Simulation with a Memory Timestamp Record

Barr, Kenneth C.; Pan, Hong; Zhang, M.; Asanović, Krste

doi:10.1109/ispass.2005.1430560

Cited by 40 publications

(33 citation statements)

References 22 publications

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“…The use of more efficient warmup techniques, such as Barr et al's memory timestamp record [4], would allow for additional speedups and could be a potential direction for future work.…”

Section: B Accurate Multi-threaded Fast-forwardingmentioning

confidence: 99%

“…This ratio directly affects the potential speedup that can be obtained from sampled simulation: as the fraction of the application simulated in detail is reduced, the simulation speed asymptotically reaches that of functional warming. Any additional gains in simulation speed will have to be made by relaxing the continuous functional warmup requirement, which is an open research problem [4].…”

Section: E Potential For Simulator Speedupmentioning

confidence: 99%

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Sampled simulation of multi-threaded applications

Carlson

Heirman

Eeckhout

2013

2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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Abstract-Sampling is a well-known workload reduction technique that allows one to speed up architectural simulation while accurately predicting performance. Previous sampling methods have been shown to accurately predict single-threaded application runtime based on its overall IPC. However, these previous approaches are unsuitable for general multi-threaded applications, for which IPC is not a good proxy for runtime. Additionally, we find that issues such as application periodicity and inter-thread synchronization play a significant role in determining how best to sample these applications.The proposed multi-threaded application sampling methodology is able to derive an effective sampling strategy for candidate applications using architecture-independent metrics. Using this methodology, large input sets can now be simulated which would otherwise be infeasible, allowing for more accurate conclusions to be made than from studies using scaled-down input sets. Through the use of the proposed methodology, we can simulate less than 10% of the total application runtime in detail. On the SPEComp, NPB and PARSEC benchmarks, running on an 8-core simulated system, we achieve an average absolute error of 3.5%.

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“…The use of more efficient warmup techniques, such as Barr et al's memory timestamp record [4], would allow for additional speedups and could be a potential direction for future work.…”

Section: B Accurate Multi-threaded Fast-forwardingmentioning

confidence: 99%

Section: E Potential For Simulator Speedupmentioning

confidence: 99%

Sampled simulation of multi-threaded applications

Carlson

Heirman

Eeckhout

2013

2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)

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“…Barr et al [1] propose the Memory Timestamp Record (MTR) to store microarchitecture state (cache and directory state) at the beginning of a sample as a checkpoint. This checkpoint can then be used to quickly restore and estimate hardware state at the beginning of each sample for different microarchitecture configurations.…”

Section: Fast Multithreaded Processor Simulationmentioning

confidence: 99%

“…Researchers and computer designers are well aware of the multicore simulation problem and have been proposing various methods for coping with it, such as sampled simulation [1], [8], [27], [29], parallelized simulation, and/ or hardware-accelerated simulation using FPGAs [5], [22], [30], or analytical modeling [10], [16], [26]. In this paper, we take a different approach through statistical simulation.…”

Section: Introductionmentioning

confidence: 99%

Chip Multiprocessor Design Space Exploration through Statistical Simulation

Genbrugge

Eeckhout

2009

IEEE Trans. Comput.

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Abstract-Developing fast chip multiprocessor simulation techniques is a challenging problem. Solving this problem is especially valuable for design space exploration purposes during the early stages of the design cycle where a large number of design points need to be evaluated quickly. This paper studies statistical simulation as a fast simulation technique for chip multiprocessor (CMP) design space exploration. The idea of statistical simulation is to measure a number of program execution characteristics from a real program execution through profiling, to generate a synthetic trace from it, and simulate that synthetic trace as a proxy for the original program. The important benefit is that the synthetic trace is much shorter compared to a real program trace, which leads to substantial simulation speedups. This paper enhances state-of-the-art statistical simulation: 1) by modeling the memory address stream behavior in a more microarchitecture-independent way and 2) by modeling a program's time-varying execution behavior. These two enhancements enable accurately modeling resource conflicts in shared resources as observed in the memory hierarchy of contemporary chip multiprocessors when multiple programs are coexecuting on the CMP. Our experimental evaluation using the SPEC CPU benchmarks demonstrates average prediction error of 7.3 percent across a range of CMP configurations while varying the number of cores and memory hierarchy configurations.

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“…Ideally, the snapshots should be microarchitecture independent, to support microarchitectural exploration with a standard set of stored snapshots. For caches, various microarchitecture-independent snapshot schemes have been proposed, which take advantage of the simple mapping of memory addresses to cache sets [1,13,27,28]. Branch predictors, however, are much more difficult to handle in the same way, as the common use of global branch histories smears the effect of a single branch address across many locations in a branch predictor.…”

Section: Introductionmentioning

confidence: 99%

Branch trace compression for snapshot-based simulation

Barr

Asanović

2006 IEEE International Symposium on Performance Analysis of Systems and Software

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We present a scheme to compress branch trace information for use in snapshot-based microarchitecture simulation. The compressed trace can be used to warm any arbitrary branch predictor's state before detailed microarchitecture simulation of the snapshot. We show that compressed branch traces require less space than snapshots of concrete predictor state. Our branch-predictor based compression (BPC) technique uses a software branch predictor to provide an accurate model of the input branch trace, requiring only mispredictions to be stored in the compressed trace file. The decompressor constructs a matching software branch predictor to help reconstruct the original branch trace from the record of mispredictions. Evaluations using traces from the Journal of ILP branch predictor competition show we achieve compression rates of 0.013-0.72 bits/branch (depending on workload), which is up to 210× better than gzip; up to 52× better than the best general-purpose compression techniques; and up to 4.4× better than recently published, more general trace compression techniques. Moreover, BPC-compressed traces can be decompressed in less time than corresponding traces compressed with other methods.

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Accelerating Multiprocessor Simulation with a Memory Timestamp Record

Abstract: We

Cited by 40 publications

References 22 publications

Sampled simulation of multi-threaded applications

Sampled simulation of multi-threaded applications

Chip Multiprocessor Design Space Exploration through Statistical Simulation

Branch trace compression for snapshot-based simulation

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