Accelerating statistical static timing analysis using graphics processing units

Gulati,; Khatri,

doi:10.1109/aspdac.2009.4796490

Cited by 38 publications

(17 citation statements)

References 13 publications

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“…Current GPUs are designed to operate in a Single Instruction Multiple Data (SIMD) fashion, which allows the simple processors to share control logic. In recent times, the application of GPUs for general purpose computations has been actively explored [23], [24], [25], [26], [30], [31]. The rapid increase in the number and diversity of scientific communities exploring the computational power of GPUs for data intensive applications has motivated GPU manufacturers to more powerful, easily programmable and flexible GPUs.…”

Section: Introductionmentioning

confidence: 99%

Highly parallel decoding of space-time codes on graphics processing units

Bollapalli

Gulati

et al. 2009

2009 47th Annual Allerton Conference on Communication, Control, and Computing (Allerton)

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Graphics Processing Units (GPUs) with a few hundred extremely simple processors represent a paradigm shift for highly parallel computations. We use this emergent GPU architecture to provide a first demonstration of the feasibility of real time ML decoding (in software) of a high rate space-time block code that is representative of codes incorporated in 4th generation wireless standards such as WiMAX and LTE. The decoding algorithm is conditional optimization which reduces to a parallel calculation that is a natural fit to the architecture of low cost GPUs.Experimental results demonstrate that asymptotically the GPU implementation is more than 700 times faster than a standard serial implementation. These results suggest that GPU architectures have the potential to improve the cost / performance tradeoff of 4th generation wireless base stations. Additional benefits might include reducing the time required for system development and the time required for configuration and testing of wireless base stations.

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Section: Introductionmentioning

confidence: 99%

Highly parallel decoding of space-time codes on graphics processing units

Bollapalli

Gulati

et al. 2009

2009 47th Annual Allerton Conference on Communication, Control, and Computing (Allerton)

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“…Paper [5] presents an implementation of Monte Carlo based SSTA using Nvidia GPUs. Their implementation is up to 2X faster than our implementation (For circuit C499, FPGA implementation is faster).…”

Section: Comparison With Gpgpu Implementationmentioning

confidence: 99%

“…But due to the high computation time, it is seldom used in practice. The work in [5] tries to accelerate conventional Monte Carlo based SSTA using graphics processing units.…”

Section: Introductionmentioning

confidence: 99%

Accelerating Monte Carlo based SSTA using FPGA

Cong

Gururaj

Liu

et al. 2010

Proceedings of the 18th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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Monte Carlo based SSTA serves as the golden standard against alternative SSTA algorithms, but it is seldom used in practice due to its high computation time. In this paper, we accelerate Monte Carlo based SSTA using the FPGA platform. A simple dataflow pipeline technique will not work well due to the excessive usage of FPGA logic slices. We leverage the recently proposed pattern matching method to identify common circuit structures, and further use a mathematical programming based formulation to explore the trade-off between performance and logic slices consumption. The proposed design provides two orders of magnitude speedup compared to the CPU-based implementation.

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“…However, all proposed GPGPU gate level simulators either do not consider timing at all (zero delay model) or only calculate the latest transition at each gate [25]. This is not sufficient for power estimation as hazards may account for up to 70% of dynamic power [26].…”

Section: Introductionmentioning

confidence: 99%

“…Gate level simulations have been accelerated using GPGPUs by parallel computation of independent gates [20], faults [21][22][23][24], or Monte-Carlo samples for statistical static timing analysis [25].…”

Section: Introductionmentioning

confidence: 99%

Scan Test Power Simulation on GPGPUs

Holst

Schneider

Wunderlich

2012

2012 IEEE 21st Asian Test Symposium

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The precise estimation of dynamic power consumption, power droop and temperature development during scan test require a very large number of time-aware gate-level logic simulations. Until now, such characterizations have been feasible only for rather small designs or with reduced precision due to the high computational demands. We propose a new, throughput-optimized timing simulator on running on GPGPUs to accelerate these tasks by more than two orders of magnitude and thus providing for the first time precise and comprehensive toggle data for industrial-sized designs and over long scan test operations. Hazards and pulse-filtering are supported for the first time in a GPGPU accelerated simulator, and the system can easily be extended to even more sophisticated delay and power models. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE. Abstract-The precise estimation of dynamic power consumption, power droop and temperature development during scan test require a very large number of time-aware gate-level logic simulations. Until now, such characterizations have been feasible only for rather small designs or with reduced precision due to the high computational demands.We propose a new, throughput-optimized timing simulator on running on GPGPUs to accelerate these tasks by more than two orders of magnitude and thus providing for the first time precise and comprehensive toggle data for industrial-sized designs and over long scan test operations. Hazards and pulse-filtering are supported for the first time in a GPGPU accelerated simulator, and the system can easily be extended to even more sophisticated delay and power models.

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Accelerating statistical static timing analysis using graphics processing units

Cited by 38 publications

References 13 publications

Highly parallel decoding of space-time codes on graphics processing units

Highly parallel decoding of space-time codes on graphics processing units

Accelerating Monte Carlo based SSTA using FPGA

Scan Test Power Simulation on GPGPUs

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