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on the affected circuit node. If the magnitude of this spike In this paper, we present a novel circuit design approach is sufficiently large, an erroneous value may be computed for radiation hardened digital electronics. Our approach is by the circuit. This is particularly problematic for memobased on the use of shadow gates, whose task it is to prories, which can flip their stored state as a result of such a tect the primary gate in case it is struck by a heavy cosmic radiation strike. Combinational logic may also be affected ion. We locally duplicate the gate to be protected, and conby such strikes, if the resulting glitch occurs at the time the nect a pair of transistors (or diodes) between the outputs circuit outputs are being sampled. Such bit reversals are reof the original and shadow gates. These transistors turn on ferred to as Single Event Upsets (SEUs) [12], or soft errors when the voltages of the two gates deviate during a radiation in the case of memory. strike. Our experiments show that at the level of a single The charge deposition rate is also referred to as the Linear gate, our circuit structure has a delay overhead of about 4% Energy Transfer (LET). Cosmic ions have varying LETs, on average, and an area overhead of over 100%. At the cirand they result in the deposition of a charge Q in a semicuit level, however, we do not need to protect all gates. We conductor diffusion region of depth t by the following forpresent a methodology to selectively protect specific gates of mula [11].the circuit in a manner that guarantees radiation tolerance for the entire circuit. With this methodology, we demon-Q= 0.01036-L t strate that at the circuzt level, the delay overhead is about 4% and the placed-and-routed area overhead is 30%, comHere L is the LET of the ion (expressed in MeV/cm2/mg), pae to an unrtce cicifr dea mape designs) t is the depth of the collection volume (expressed in microns), and Q is charge in pC. The amount of charge that Categories and Subject Descriptors: B.8.2 [Performance is required to cause a bit to be sampled incorrectly is reand Reliability]: Reliability, Testing, and Fault-Tolerance ferred to as the critical charge, Qc [13]. With diminishing General Terms: Design, Reliability process feature sizes and supply voltages, SEU problems are

The current work describes a new standing wave oscillator scheme aimed for clock propagation on coplanar transmission lines on a silicon die. The design is aimed for clock signaling in the Gigahertz range (we are able to achieve clock rates of 8GHz and above). The clock is transported as an oscillatory wave on a pair of conductors. An oscillatory standing wave is formed across a transmission line loop, which is connected beginning-to-end through a Mobius configuration. A single cross coupled inverter pair is required to maintain oscillation across the ring. The design is aimed to achieve low skew, low power and extreme high frequency global clock situations. The energy recycling nature of a standing wave along a transmission line allows us to keep very high frequencies oscillations along a conductor with almost no power consumption at all. A special wide input range driver was designed to convert the differential signals on the coplanar transmission lines into a square clock pulse for standard clock sinks. The design uses CMOS 90nm BSim3v model cards for all simulations, with the transmission lines implemented on Metal8.

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