Acceleration of HMM-based speech recognition system by parallel FPGA Gaussian calculation

Abstract

An FPGA-based custom core which computes the Gaussian calculation portion of a Hidden Markov Model (HMM) based speech recognition system, is presented. The work is part of the development of a custom embedded system which will provide speaker independend, large vocabulary continuos speech recognition and is currently presented as a hardware/software codesign. By de-coupling the Gaussian calculation from the backend search, calculation of Gaussian results is performed with minimal communication between backend search software and an FPGA based Gaussian core. Several implementations have been investigated in order to minimize memory bandwidth and FPGA resource requirements and are presented. The system has been implemented using an Alpha Data XCR-5T1, reconfigurable computer housing a Virtex 5 SX95T FPGA and has achieved better than real-time performance at 133MHz. The core has been tested and is capable of calculating a full set of Gaussian results from 3825 acoustic models in 5.3ms which coupled with a backend search of 5000 words has provided over 80% accuracy.

FPGA Implementation of a Pipelined Gaussian Calculation for HMM-Based Large Vocabulary Speech Recognition

“…Performance figures are given for two implementations. The first case, which was originally presented in [12], has been implemented in C++ compiled with Microsoft compilers via Visual Studio 2008. This implementation achieves speeds of 114 frames per second on average which is better than the real-time figure of 100 frames per second.…”

“…For this reason, the approach taken in designing the Gaussian core was to first build a single, efficient pipeline with minimal control and then to build a parallel architecture containing multiple pipelines which could be configured to achieve specific design goals. In this section, we will first present the single core implementation which was first proposed in the previous paper [12] and then describe a number of new multi-core architectures that have been implemented since the original publication, in order to provide a solution tailored to the required performance of a range of speech recognition systems.…”

“…The first is based on a buffered input system and is new for this paper. The second was first proposed in [12] and uses parallel acoustic models on a single Acoustic Observation Vector.…”

“…This work, originally presented at the 6th Southern Programmable Logic Conference [12], outlined the Gaussian core as a hardware peripheral capable of real-time operation; dual cores were implemented in order to achieve this. Improvements to that paper that have been included here are given below.…”

Upgrading FPGA Implementation of Isolated Word Recognition System for a Real-Time Operation

“…The recognition of large vocabulary and continuous speech requires complicated algorithms with huge amounts of calculations, large quantities of memory [3], [4]. This can result in enlarged power consumption, longer recognition time and higher recognition error rate.…”