Access order to avoid inter-vector-conflicts in complex memory systems

Corral, A. M. del; Llaberia, J.M.

doi:10.1109/ipps.1995.395963

Cited by 4 publications

(2 citation statements)

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“…They analyze this system first for single vectors [18], and then extend the work for multiple vectors [15]. del Corral and Llaberia analyze a related hardware scheme for avoiding bank conflicts among multiple vectors in complex memory systems [8]. These access-scheduling schemes focus on memory systems composed of SRAM components (with uniform access time), and thus they do not address precharge delays and open-row policies.…”

Section: Related Workmentioning

confidence: 99%

Algorithmic foundations for a parallel vector access memory system

Mathew

McKee

Carter

et al. 2000

Proceedings of the Twelfth Annual ACM Symposium on Parallel Algorithms and Architectures

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This paper presents mathematical foundations for the design of a memory controller subcomponent that helps to bridge the processor/memory performance gap for applications with strided access patterns. The Parallel Vector Access (PVA) unit exploits the regularity of vectors or streams to access them efficiently in parallel on a multi-bank SDRAM memory system. The PVA unit performs scatter/gather operations so that only the elements accessed by the application are transmitted across the system bus. Vector operations are broadcast in parallel to all memory banks, each of which implements an efficient algorithm to determine which vector elements it holds. Earlier performance evaluations have demonstrated that our PVA implementation loads elements up to 32.8 times faster than a conventional memory system and 3.3 times faster than a pipelined vector unit, without hurting the performance of normal cache-line fills. Here we present the underlying PVA algorithms for both word interleaved and cache-line interleaved memory systems.

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Section: Related Workmentioning

confidence: 99%

Algorithmic foundations for a parallel vector access memory system

Mathew

McKee

Carter

et al. 2000

Proceedings of the Twelfth Annual ACM Symposium on Parallel Algorithms and Architectures

View full text Add to dashboard Cite

show abstract

“…They analyze this system first for single vectors [24], and then extend the design to multiple vectors [25]. del Corral and Llaberia analyze a related hardware scheme for avoiding bank conflicts among multiple vectors in complex memories [7]. These schemes focus on vector computers with (uniform access time) SRAM memory components.…”

Section: Related Workmentioning

confidence: 99%

Design of a parallel vector access unit for SDRAM memory systems

Mathew

McKee²,

Carter³

et al.

Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550)

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Dynamic access ordering for streamed computations

McKee

Wulf

Aylor

et al. 2000

IEEE Trans. Comput.

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ÐMemory bandwidth is rapidly becoming the limiting performance factor for many applications, particularly for streaming computations such as scientific vector processing or multimedia (de)compression. Although these computations lack the temporal locality of reference that makes traditional caching schemes effective, they have predictable access patterns. Since most modern DRAM components support modes that make it possible to perform some access sequences faster than others, the predictability of the stream accesses makes it possible to reorder them to get better memory performance. We describe a Stream Memory Controller (SMC) system that combines compile-time detection of streams with execution-time selection of the access order and issue. The SMC effectively prefetches read-streams, buffers write-streams, and reorders the accesses to exploit the existing memory bandwidth as much as possible. Unlike most other hardware prefetching or stream buffer designs, this system does not increase bandwidth requirements. The SMC is practical to implement, using existing compiler technology and requiring only a modest amount of specialpurpose hardware. We present simulation results for fast-page mode and Rambus DRAM memory systems and we describe a prototype system with which we have observed performance improvements for inner loops by factors of 13 over traditional access methods.

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Access order to avoid inter-vector-conflicts in complex memory systems

Cited by 4 publications

References 4 publications

Algorithmic foundations for a parallel vector access memory system

Algorithmic foundations for a parallel vector access memory system

Design of a parallel vector access unit for SDRAM memory systems

Dynamic access ordering for streamed computations

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