Design of a parallel vector access unit for SDRAM memory systems

Mathew, Beena; McKee, Sally A.; Carter, J.B.; Davis, Al

doi:10.1109/hpca.2000.824337

Cited by 36 publications

(35 citation statements)

References 14 publications

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“…One key idea is to group together memory accesses with the same access type and similar addresses by reordering, in order to minimize the performance degradation due to various timing constraints on DRAM accesses. There have been proposals to exploit these characteristics to achieve higher performance on vector [21], stream [32], and single-core and multicore processors [26,27]. Higher performance typically leads to higher energy efficiency by reducing execution time and saving static power.…”

Section: Related Workmentioning

confidence: 99%

Future scaling of processor-memory interfaces

Ahn

Jouppi

Kozyrakis

et al. 2009

Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis

105

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Continuous evolution in process technology brings energyefficiency and reliability challenges, which are harder for memory system designs since chip multiprocessors demand high bandwidth and capacity, global wires improve slowly, and more cells are susceptible to hard and soft errors. Recently, there are proposals aiming at better main-memory energy efficiency by dividing a memory rank into subsets.We holistically assess the effectiveness of rank subsetting in the context of system-wide performance, energy-efficiency, and reliability perspectives. We identify the impact of rank subsetting on memory power and processor performance analytically, then verify the analyses by simulating a chipmultiprocessor system using multithreaded and consolidated workloads. We extend the design of Multicore DIMM, one proposal embodying rank subsetting, for high-reliability systems and show that compared with conventional chipkill approaches, it can lead to much higher system-level energy efficiency and performance at the cost of additional DRAM devices.

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Section: Related Workmentioning

confidence: 99%

Future scaling of processor-memory interfaces

Ahn

Jouppi

Kozyrakis

et al. 2009

Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis

105

View full text Add to dashboard Cite

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“…In technology, DRAM latency is improved by 7% every year, which is much slower than that of processor. In computer architecture, many architecture-level mechanisms have been employed or studied at the DRAM level to improve performance, such as latency reduction and data transfer rate improving techniques [50,20,21,40,41,39,45,46], and memory access scheduling [44,36,35,37,38,17,49,48,5,59,34,58,7,60,19,47,53].…”

Section: Thermal Issue Of Ddr2 and Fully Buffered Dimm (Fbdimm) Memoriesmentioning

confidence: 99%

Thermal modeling and management of DRAM memory systems

LinJiang

ZhengHongzhong

ZhuZhichun

et al. 2007

SIGARCH Comput. Archit. News

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With increasing speed and power density, high-performance memories, including FB-DIMM (Fully Buffered DIMM) and DDR2 DRAM, now begin to require dynamic thermal management (DTM) as processors and hard drives did. The DTM of memories, nevertheless, is different in that it should take the processor performance and power consumption into consideration. Existing schemes have ignored that. In this study, we investigate a new approach that controls the memory thermal issues from the source generating memory activities - the processor. It will smooth the program execution when compared with shutting down memory abruptly, and therefore improve the overall system performance and power efficiency. For multicore systems, we propose two schemes called adaptive core gating and coordinated DVFS. The first scheme activates clock gating on selected processor cores and the second one scales down the frequency and voltage levels of processor cores when the memory is to be over-heated. They can successfully control the memory activities and handle thermal emergency. More importantly, they improve performance significantly under the given thermal envelope. Our simulation results show that adaptive coregating improves performance by up to 23.3% (16.3% on average) on a four-core system with FB-DIMM when compared with DRAM thermal shutdown; and coordinated DVFS with control-theoretic methods improves the performance by up to 18.5% (8.3% on average).

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“…However, it has been shown that better memory scheduling approaches can substantially improve performance [30,6,28,33,16]. Such approaches improve performance by reducing gaps between commands.…”

Section: Related Workmentioning

confidence: 99%