Thermal modeling and management of DRAM memory systems

Abstract

With increasing speed and power density, high-performance memories, including FB-DIMM (Fully Buffered DIMM) and DDR2 DRAM, now begin to require dynamic thermal management (DTM) as processors and hard drives did. The DTM of memories, nevertheless, is different in that it should take the processor performance and power consumption into consideration. Existing schemes have ignored that. In this study, we investigate a new approach that controls the memory thermal issues from the source generating memory activities - the processor. It will smooth the program execution when compared with shutting down memory abruptly, and therefore improve the overall system performance and power efficiency. For multicore systems, we propose two schemes called adaptive core gating and coordinated DVFS. The first scheme activates clock gating on selected processor cores and the second one scales down the frequency and voltage levels of processor cores when the memory is to be over-heated. They can successfully control the memory activities and handle thermal emergency. More importantly, they improve performance significantly under the given thermal envelope. Our simulation results show that adaptive coregating improves performance by up to 23.3% (16.3% on average) on a four-core system with FB-DIMM when compared with DRAM thermal shutdown; and coordinated DVFS with control-theoretic methods improves the performance by up to 18.5% (8.3% on average).

Memory power management via dynamic voltage/frequency scaling

“…Lin et al [21,22] propose two thermal-motivated mechanisms, both of which throttle the CPU to reduce memory traffic. The first, adaptive core gating, uses clock-gating on processor cores when memory nears its thermal limit; the second, coordinated DVFS, uses DVFS to slow the cores in the same situation.…”

Energy efficient proactive thermal management in memory subsystem

“…To handle thermal problems in memory subsystem, a few techniques have been suggested [11,10]. The work in [11] mitigates overheating in memory system by adjusting memory throughput to stay below the emergency level.…”

“…The work in [11] mitigates overheating in memory system by adjusting memory throughput to stay below the emergency level. The primary drawback in this approach is the associated performance overhead.…”

A power and temperature aware DRAM architecture

“…We utilize a RC-analogy based thermal model widely used in literature for the DRAM system, which is also similar to the model presented by Lin et al [8]. We present static temperature values for each workload.…”

“…We present static temperature values for each workload. We also adopted the AMB power model used by Lin et al [8]. We have estimated the power consumption of PHA-WB by modeling the broadcast structure and the buffer array using CACTI 3.2 [14].…”