Algorithmic foundations for a parallel vector access memory system

Abstract

This paper presents mathematical foundations for the design of a memory controller subcomponent that helps to bridge the processor/memory performance gap for applications with strided access patterns. The Parallel Vector Access (PVA) unit exploits the regularity of vectors or streams to access them efficiently in parallel on a multi-bank SDRAM memory system. The PVA unit performs scatter/gather operations so that only the elements accessed by the application are transmitted across the system bus. Vector operations are broadcast in parallel to all memory banks, each of which implements an efficient algorithm to determine which vector elements it holds. Earlier performance evaluations have demonstrated that our PVA implementation loads elements up to 32.8 times faster than a conventional memory system and 3.3 times faster than a pipelined vector unit, without hurting the performance of normal cache-line fills. Here we present the underlying PVA algorithms for both word interleaved and cache-line interleaved memory systems.

Parallel 2D FFT implementation on FPGA suitable for real-time MR image processing

“…Many methods for multiple accesses to memory for parallel and distributed operations of an algorithm have been reported. [26][27][28][29][30][31][32][33][34][35][36][37] In our work, a data management unit (DMU) is used to schedule all requests for transferring data between the FIFO buffers and on-chip memory. The DMU consists mainly of multiple address generation units (AGUs) used to control reading and writing access to on-chip memory.…”

Collective Memory Transfers for Multi-Core Chips

“…Classic vector machines such as the Cray-1 [61,50] overcome the inefficiencies of DRAM overfetch and access granularity by using massive bank-switching to offer wordgranularity accesses. However, vector core designs and memory controllers are costly due to their limited market and sizable engineering costs [24].…”

High-bandwidth Address Generation Unit

“…An extension of the work presented in [9] is proposed by Mathew et al in [10,11] where the authors proposed a Parallel Vector Access unit (PVA). This unit is a vector memory subsystem that provided strided data accesses with high efficiency on a multi-module SDRAM memory.…”