AccuPower: an accurate power estimation tool for superscalar microprocessors

Ponomarev, Dmitry; Küçük, Gürhan; Ghose, K.

doi:10.1109/date.2002.998259

Cited by 20 publications

(10 citation statements)

References 13 publications

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“…To evaluate the power savings achieved in the IQ by the use of the proposed mechanisms, we used the AccuPower toolset [13]. The widely-used Simplescalar simulator [14] was significantly modified (the code for dispatch, issue, writeback and commit steps was written from scratch) to implement true hardware level, cycle-by-cycle simulation models for such datapath components as the IQ, the reorder buffer, physical register files, architectural register files and the rename table.…”

Section: Evaluation Methodologymentioning

confidence: 99%

Energy-efficient issue queue design

Ponomarev

Küçük

Ergin

et al. 2003

IEEE Trans. VLSI Syst.

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Abstract-The out-of-order issue queue (IQ), used in modern superscalar processors is a considerable source of energy dissipation. We consider design alternatives that result in significant reductions in the power dissipation of the IQ (by as much as 75%) through the use of comparators that dissipate energy mainly on a tag match, 0-B encoding of operands to imply the presence of bytes with all zeros and, bitline segmentation. Our results are validated by the execution of SPEC 95 benchmarks on a true hardware level, cycle-by-cycle simulator for a superscalar processor and SPICE measurements for actual layouts of the IQ in a 0.18-m CMOS process.Index Terms-Bitline segmentation, low-power comparator, low-power instruction scheduling, low-power superscalar datapath.

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Section: Evaluation Methodologymentioning

confidence: 99%

Energy-efficient issue queue design

Ponomarev

Küçük

Ergin

et al. 2003

IEEE Trans. VLSI Syst.

Self Cite

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show abstract

“…This error is due to several reasons, such as, the different processor parameters of the two processors and the inaccuracy of the simplescalar model (Wattch is built on top of Simplescalar) for reporting cache misses. In addition, it is also known that processor energy calculation using processor model derived from simplescalar is inaccurate; for example, simplescalar modeled the issue queue, reorder buffer, and the physical register file as a unified structure called Register Update Unit (RUU), unlike in real implementations where the number of entries and the number of ports in all these components are quite disparate [20]. We also performed simulation with Wattch for the remaining Mediabench benchmarks and obtained similar energy graph results in comparison to energy graph obtain from using Equation 2.…”

Section: Model Validationmentioning

confidence: 99%

Finding optimal L1 cache configuration for embedded systems

Janapsatya

Ignjatović

Parameswaran

2006

Proceedings of the 2006 Conference on Asia South Pacific Design Automation - ASP-DAC '06

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Modern embedded system execute a single application or a class of applications repeatedly. A new emerging methodology of designing embedded system utilizes configurable processors where the cache size, associativity, and line size can be chosen by the designer. In this paper, a method is given to rapidly find the L1 cache miss rate of an application. An energy model and an execution time model are developed to find the best cache configuration for the given embedded application. Using benchmarks from Mediabench, we find that our method is on average 45 times faster to explore the design space, compared to Dinero IV while still having 100% accuracy.

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“…We used the AccuPower toolset [15] to evaluate the effects of the proposed architecture on the performance, power dissipation and the overall complexity of the ROB. The widely-used Simplescalar simulator [1] was significantly modified (the code for dispatch, issue, writeback and commit steps was written from scratch) to implement true hardware level, cycle-by-cycle simulation models for such datapath components as the ROB (integrating a physical register file), the issue queue, and the rename table.…”

Section: Simulation Environmentmentioning

confidence: 99%

Low-complexity reorder buffer architecture

Küçük

Ponomarev

Ghose

2002

Proceedings of the 16th International Conference on Supercomputing

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In some of today's superscalar processors (e.g.the Pentium III), the result repositories are implemented as the Reorder Buffer (ROB) slots. In such designs, the ROB is a complex multi-ported structure that occupies a significant portion of the die area and dissipates a non-trivial fraction of the total chip power, as much as 27% according to some estimates. In addition, an access to such ROB typically takes more than one cycle, impacting the IPC adversely.We propose a low-complexity and low-power ROB design that exploits the fact that the bulk of the source operand values is obtained through data forwarding to the issue queue or through direct reads of the committed register values. Our ROB design uses an organization that completely eliminates the read ports needed to read out operand values for instruction issue. Any consequential performance degradation is countered by using a small number of associatively-addressed retention latches to hold the most recent set of values written into the ROB. The contents of the retention latches are used to satisfy the operand reads for issue that would otherwise have to be read from the ROB slots. Significant savings of the ROB real estate as well as power savings in the range of 20% to 30% for the ROB are achieved using the proposed technique. At the same time, the fact that results are accessible in a single cycle from the retention latches actually leads to an overall improvement in the IPC of up to 3% on the average for SPEC 2000 benchmarks.

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AccuPower: an accurate power estimation tool for superscalar microprocessors

Abstract: Abstract

Cited by 20 publications

References 13 publications

Energy-efficient issue queue design

Energy-efficient issue queue design

Finding optimal L1 cache configuration for embedded systems

Low-complexity reorder buffer architecture

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