Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks

Konuk, H.

doi:10.1109/dac.1995.249971

Cited by 3 publications

References 15 publications

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Charge-based fault simulation for CMOS network breaks

Konuk

Ferguson

Larrabee

1996

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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We de ne a network break as a break fault in the p-network or in the n-network of a CMOS cell that breaks one or more transistor paths between the cell output and Vdd or GND. Previous work, mostly in the context of transistor stuck-open faults, studied test invalidation due to transient paths to Vdd or GND, and due to charge sharing. In this paper we show the importance of Miller feedthrough and feedback capacitances in network break test invalidation, which was ignored by previous work. We present a new fault simulation algorithm for network breaks, with the following novelties: First, the electrical charge coming from Miller and pn junction capacitances is computed using a transistor charge model 18]; this automatically handles the non-linear nature of transistor capacitances accurately, as opposed to assuming constant capacitance values as was done in previous work. Next, we use only six voltage levels for charge computations, which allows us to create look-up tables that dramatically reduce the computation time. Finally, the maximum voltage an internal node in an n-network can acquire is about three-fourths of the Vdd voltage (instead of Vdd as assumed by previous work), and similarly, a p-network node cannot discharge all the way down to the GND voltage.Using our simulator to analyze test sets for the ISCAS85 circuits, we found that the charge coming from Miller capacitances has a larger share in test invalidation than the charge from p-n junction capacitances. Our simulator spends less time for charge computations than it spends for transient path identi cation.

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Charge-based fault simulation for CMOS network breaks

Konuk

Ferguson

Larrabee

1996

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits

Konuk

Ferguson

1998

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Shorts and opens are the most common types of catastrophic defects in today's CMOS ICs. In this paper we show that an open in the interconnect wiring of a digital CMOS circuit, which permanently disconnects inputs of logic gates from their driver, can cause oscillation or sequential behavior. We present supporting experimental data collected by creating an interconnect open in a manufactured chip. We also show that the conditions for oscillation and sequential behavior are likely to occur in many interconnect opens.

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Resistive Bridging Fault Simulation of Industrial Circuits

Engelke¹,

Polian²,

Schloeffel³

et al. 2008

2008 Design, Automation and Test in Europe

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We report the successful application of a resistive bridging fault (RBF) simulator to industrial benchmark circuits. Despite the slowdown due to the consideration of the sophisticated RBF model, the run times of the simulator were within an order of magnitude of the run times for pattern-parallel complete-circuit stuck-at fault simulation. Industrial-size circuits, including a multi-million-gates design, could be simulated in reasonable time despite a significantly higher number offaults to be simulated compared with stuck-atfault simulation.

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Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks

Cited by 3 publications

References 15 publications

Charge-based fault simulation for CMOS network breaks

Charge-based fault simulation for CMOS network breaks

Oscillation and sequential behavior caused by opens in the routing in digital CMOS circuits

Resistive Bridging Fault Simulation of Industrial Circuits

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