Accurate characterization and understanding of interface trap density trends between atomic layer deposited dielectrics and AlGaN/GaN with bonding constraint theory

Abstract

Many dielectrics have been proposed for the gate stack or passivation of AlGaN/GaN based metal oxide semiconductor heterojunction field effect transistors, to reduce gate leakage and current collapse, both for power and RF applications. Atomic Layer Deposition (ALD) is preferred for dielectric deposition as it provides uniform, conformal, and high quality films with precise monolayer control of film thickness. Identification of the optimum ALD dielectric for the gate stack or passivation requires a critical investigation of traps created at the dielectric/AlGaN interface. In this work, a pulsed-IV traps characterization method has been used for accurate characterization of interface traps with a variety of ALD dielectrics. High-k dielectrics (HfO2, HfAlO, and Al2O3) are found to host a high density of interface traps with AlGaN. In contrast, ALD SiO2 shows the lowest interface trap density (<2 × 1012 cm−2) after annealing above 600 °C in N2 for 60 s. The trend in observed trap densities is subsequently explained with bonding constraint theory, which predicts a high density of interface traps due to a higher coordination state and bond strain in high-k dielectrics.

Electrical hysteresis in p-GaN metal–oxide–semiconductor capacitor with atomic-layer-deposited Al2O3 as gate dielectric

“…6) Among various deposition techniques, 7,8) atomic layer deposition (ALD) is widely used, as its sequential self-terminating reaction provides homogeneous, conformal, and high-quality films with precise monolayer control of the film thickness. 6) Although there are many investigations on the ALD-Al 2 O 3 =n-GaN MOS structures, 8) there are no studies on the electrical hysteresis in an ALD-Al 2 O 3 =p-GaN MOS structure have been reported. Since the surface features of p-GaN and their effects on the properties of dielectric=p-GaN differ from those of n-GaN, 9,10) investigations of the electrical hysteresis of the Al 2 O 3 =p-GaN structure and the hole trapping and detrapping processes are in great demand for the development of p-GaN-related MOS devices.…”

ALD gate dielectrics for improved threshold voltage stability in AlGaN/GaN MOS-HFETs for power applications

“…Clockwise hysteresis indicates electron trapping and de-trapping at the dielectric/AlGaN interface traps. The size of the hysteresis window, for each ALD dielectric, is found to be proportional to the density of dielectric/AlGaN interface traps characterized on the same samples in [17] as HfAlO≈HfO 2 >Al 2 O 3 >SiO 2 , also shown in figure 6 inset. Such high densities of interface traps with high-k dielectrics are expected, according to bonding constraint theory [17].…”

“…In our recent work [17,18], we have characterized MOS-HFETs with different popular high-k (HfO 2 , HfAlO, Al 2 O 3 ) and low-k (SiO 2 ) ALD gate dielectrics for interface traps with AlGaN/GaN. In this work, we correlate the trends in threshold voltage stability with the extracted trap densities in [17]. Additionally, a comprehensive study of threshold voltage magnitudes is used to extract interface and bulk dielectric fixed charge densities.…”

Off-state drain leakage reduction by post metallization annealing for Al2 O3 /GaN/AlGaN/GaN MOSHEMTs on Si

“…In order to block the gate leakage current and suppress the drain current collapse, the Al 2 O 3 gate dielectric by atomic layer deposition (ALD) has been adopted to form metal‐oxide‐semiconductor HEMTs (MOSHEMTs) . However, adding an insulator between the gate metal and barrier layer creates an extra dielectric/(Al)GaN interface, which could introduce high density donor‐like interface traps . These trap states can assist the two‐dimensional variable range hopping (2D‐VRH) conduction, resulting in serious surface leakage current through the interface .…”