Accurate Estimation of SRAM Dynamic Stability

Khalil, Diaa; Khellah, Muhammad; Kim, Nam-Sung; Ismail, Yehea; Karnik, Tanay; De, Vivek

doi:10.1109/tvlsi.2008.2001941

Cited by 72 publications

(33 citation statements)

References 23 publications

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“…Fig. 8 plots the correlation between dynamic write stability [2] and static bitline write margin (BLWM) [5] for 1024 cells. Correlation between dynamic and static write margin is only observed at V DD,low (Fig.…”

Section: Implementation and Resultsmentioning

confidence: 99%

“…Introduction Static (DC) noise margins are often used to characterize SRAM because of their simple interpretation and measurements, although they overestimate read failures and underestimate write failures. Alternately, dynamic SRAM stability has been proposed to be characterized by using critical wordline pulse width, which produces better estimates of failure rates [1][2][3], but this method has not been compared with static margins. This work demonstrates the on-chip circuitry for characterizing dynamic SRAM stability using wordline pulses with accuracy better than 10ps.…”

mentioning

confidence: 99%

“…Fig. 7 plots statistical distributions of dynamic read stability [2]. The SRAM cells are biased with extra read stress, as indicated in Fig.…”

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confidence: 99%

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Dynamic SRAM stability characterization in 45nm CMOS

Toh

Guo

Nikolić

2010

2010 Symposium on VLSI Circuits

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A method for characterizing dynamic SRAM stability using pulsed wordlines, is demonstrated in 45nm CMOS. Static read margins were observed to overestimate failures by up to 1000x while static write margins failed to predict outliers in dynamic write stability. Dynamic write stability was demonstrated to exhibit an enhanced sensitivity to process variations, and negative bias temperature instability (NBTI), compared to static write margins. Introduction Static (DC) noise margins are often used to characterize SRAM because of their simple interpretation and measurements, although they overestimate read failures and underestimate write failures. Alternately, dynamic SRAM stability has been proposed to be characterized by using critical wordline pulse width, which produces better estimates of failure rates [1][2][3], but this method has not been compared with static margins. This work demonstrates the on-chip circuitry for characterizing dynamic SRAM stability using wordline pulses with accuracy better than 10ps. Fig. 1 shows the SRAM array configuration for the characterization of the dynamic metrics and the necessary infrastructure for collecting static metrics for the purpose of establishing correlations between the measured results. A pulse of programmable width is generated centrally and delivered to a wordline following the row decoders. To avoid process-and layout-induced uncertainties, the exact pulse width is measured by wordline samplers located on every wordline. Each sampler consists of a high bandwidth dual-phase-clocked track-and-hold circuit followed by a comparator with offset calibration. The use of dual-phase-clocked track-and-hold circuits as well as calibration of the phase of these dual-phase clocks is essential for sampling the fast rising and falling transitions of wordline pulses with minimal distortion. This calibration scheme produces finer resolution compared to delay-line based schemes [4]. All array bitlines are accessible externally through a bitline switch network using 4-terminal Kelvin sensing to bias the bitline voltages during dynamic stability measurements as well as to characterize static read and write SRAM metrics [5]. Fig. 2 illustrates key circuit blocks for enabling accurate on-chip pulse generation. Two clock signals with a slight difference in clock period (ΔT) are used to produce a pulse train with a pulse width difference of ΔT between successive pulses. A counter is then used to select the desired pulse, based on a programmed digital codeword. This counter is synchronized by a sync signal which is asserted when Φ 0 and Φ 1 have the desired phase relationship. Phase calibration of the sampling edges of the wordline samplers is accomplished by capacitively summing both sampling edges and adjusting the skew between them to reduce the glitch on the summing node. A Monte Carlo simulation of this scheme reveals that it reduces the phase offset of respective edges to less than 3 ps. The impact of clock jitter on measurement accuracy is reduced through averaging. The b...

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Section: Implementation and Resultsmentioning

confidence: 99%

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confidence: 99%

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Dynamic SRAM stability characterization in 45nm CMOS

Toh

Guo

Nikolić

2010

2010 Symposium on VLSI Circuits

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“…Starting with an initial logic state, an event is applied to the SRAM cell -be it a cell access (read or write) or a noise event (SEU). Following the completion of the event, if the state of the cell is as expected (the same as before for hold and read or flipped for write), the cell is found to be dynamically stable [13]. Estimation of dynamic stability is generally done at both a single cell level for fast, many sample statistical (MC) simulations, and at a full block level for thorough analysis that takes into consideration all factors.…”

Section: Dynamic Stability and Dynamic Noise Marginsmentioning

confidence: 99%

Dynamic stability and noise margins of SRAM arrays in nanoscaled technologies

Teman

2014

2014 IEEE Faible Tension Faible Consommation

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Abstract-SRAM stability is one of the primary bottlenecks of current VLSI system design, and the unequivocal supply voltage scaling limiter. Static noise margin metrics have long been the de-facto standard for measuring this stability and estimating the yield of SRAM arrays. However, in modern process technologies, under scaled supply voltages and increased process variations, these traditional metrics are no longer sufficient. Recent research has analyzed the dynamic behavior and stability of SRAM circuits, leading to dynamic stability metrics and dynamic noise margin definition. This paper provides a brief overview of the limitations of static noise margin metrics and the resulting dynamic stability and noise margin concepts that have been proposed to overcome them.

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“…In practice, wordlines are pulsed for a short amount of time, during which the cells are written and read. There is a recent trend in assessing dynamic SRAM read/write margins, for more accurate estimation of the necessary operating voltages [40].…”

Section: Sram Characterizationmentioning

confidence: 99%

Technology variability from a design perspective

Nikolić

Giraud

Guo

et al. 2010

IEEE Custom Integrated Circuits Conference 2010

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Increased variability in semiconductor process technology and devices requires added margins in the design to guarantee the desired yield. Variability is characterized with respect to the distribution of its components, its spatial and temporal characteristics and its impact on specific circuit topologies. Approaches to variability characterization and modeling for digital logic and SRAM are reviewed in this paper. Transistor and ring oscillator arrays are designed to isolate specific systematic and random variability components in the design. Distributions of SRAM design margins are measured by padded-out cells and minimum operating voltages for the entire array. Correlations between various components of variability are essential for adding appropriate margins to the design.

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Accurate Estimation of SRAM Dynamic Stability

Cited by 72 publications

References 23 publications

Dynamic SRAM stability characterization in 45nm CMOS

Dynamic SRAM stability characterization in 45nm CMOS

Dynamic stability and noise margins of SRAM arrays in nanoscaled technologies

Technology variability from a design perspective

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