Adaptive Cache Compression for High-Performance Processors

Alameldeen, Alaa R.; Wood, David А.

doi:10.1145/1028176.1006719

Cited by 118 publications

(211 citation statements)

References 39 publications

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“…Such techniques try to exploit different characteristics of the address/data streams to achieve high compression ratios [1,11,14,15]. One direction concentrates on exploiting the well known phenomenon of locality and especially value locality.…”

Section: The Dynamic Behavior Of Frequent Valuesmentioning

confidence: 99%

“…As of yet, no mechanism has been proposed to implement a dynamic dictionary for caches; instead the dictionaries proposed so far are loaded statically via profiling or are "trained" for a small period of time but remain static once they are loaded with values [1,14,23,25,26]. Dynamic (adaptive) dictonaries are reported in the context of bus compression [2,7,17,19,20,24].…”

Section: Dynamic Dictionary and Compressed Data Consistencymentioning

confidence: 99%

“…This is easily attainable in the L2 or L3 caches where the compression/decompression costs compare favourably (i.e. are much lower) to the cost of going to main memory [1,11,14,15]. The same is true for main memory with respect to the long disc delays and this is why many proposals consider main memory compression [6].…”

Section: Introductionmentioning

confidence: 99%

“…The reason is that it almost always pays to have a "bigger" cache: Alameldeen and Wood [1] show that in commercial applications where the miss rate is relatively high, compression of the L2, regardless of its size, is beneficial. Furthermore, we are fast moving towards multiple cores on a chip, which will exacerbate the problem of adequate cache capacity since the cache will have to be shared by many applications or threads.…”

Section: Introductionmentioning

confidence: 99%

“…In addition, at the top level of the hierarchy, compression/decompression costs of the order of 10 to 15 cycles approach L2 access latencies, which means that accessing a compressed L1 datum (that would be a miss) has little difference from going directly to the L2. Thus, latency alone rules out all complex compression/decompression schemes such as those used in L2 compression [1,11,14,15]. Power consumption is also becoming a critical issue in L1.…”

Section: Introductionmentioning

confidence: 99%

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Dynamic Dictionary-Based Data Compression for Level-1 Caches

Κεραμίδας

Aisopos

2006

Architecture of Computing Systems - ARCS 2006

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Abstract. Data cache compression is actively studied as a venue to make better use of onchip transistors, increase apparent capacity of caches, and hide the long memory latencies. While several techniques have been proposed for L2 compression, L1 compression is an elusive goal. This is due to L1's sensitivity to latency and the inability to create compression schemes that are both fast and adaptable to program behavior, i.e. dynamic. In this paper, we propose the first dynamic dictionary-based compression mechanism for L1 data caches. Our design solves the problem of keeping the compressed contents of the cache and the dictionary entries consistent, using a timekeeping decay technique. A dynamic compression dictionary adapts to program behavior without the need of profiling techniques and/or training phases. We compare our approach to previously proposed static dictionary techniques and we show that we surpass them in terms of power, hit ratio and energy delay product.

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Section: The Dynamic Behavior Of Frequent Valuesmentioning

confidence: 99%

Section: Dynamic Dictionary and Compressed Data Consistencymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Dynamic Dictionary-Based Data Compression for Level-1 Caches

Κεραμίδας

Aisopos

2006

Architecture of Computing Systems - ARCS 2006

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Reducing Cache Hardware by Focusing on Data Redundancy

Kobayashi

Matsukawa

Shimomura

et al. 2014

Elect Comm in Japan

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SUMMARY There is one reason to utilize cache that mitigates processor performance limitation comes from data transfer bandwidth. Recently, cache size expansion is required in this use because data transfer bandwidth requirement is increasing for recent large data size and multi‐core trends. However, cache size expansion is unwelcome because it causes problems arising from circuit area and power consumption viewpoint. This paper focuses a data redundancy with the goal of reducing cache size and proposes a mechanism that does not store redundant data into cache. The proposed mechanism divides data into higher bit and lower bit that stored into higher cache and lower cache, respectively. We reduced higher cache size to half size by keeping 46% redundant data in higher bit area not to store into higher cache. The evaluation results show that the proposed mechanism increases IPC by 3.3% on average compared with same circuit area conventional cache under SPECCPU2000 benchmarks.

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