Adaptive cache compression for non-volatile memories in embedded system

Choi, Ju Hee; Kwak, Jong Wook; Jhang, Seong Tae; Jhon, Chu Shik

doi:10.1145/2663761.2663764

Cited by 6 publications

(6 citation statements)

References 19 publications

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“…In general, by reducing the amount of data written to memory system, compression may improve the performance and lifetime of NVMs. However, (de)compression can generate additional write operations [31], which may harm NVM lifetime. For these reasons, careful management is required to realize the full potential of compression in NVMs.…”

Section: Factors and Tradeoffs In Compressionmentioning

confidence: 99%

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A Survey Of Architectural Approaches for Data Compression in Cache and Main Memory Systems

Mittal

Vetter

2016

IEEE Trans. Parallel Distrib. Syst.

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As the number of cores on a chip increase and key applications become even more data-intensive, memory systems in modern processors have to deal with increasingly large amount of data. In face of such challenges, data compression presents as a promising approach to increase effective memory system capacity and also provide performance and energy advantages. This paper presents a survey of techniques for using compression in cache and main memory systems. It also classifies the techniques based on key parameters to highlight their similarities and differences. It discusses compression in CPUs and GPUs, conventional and non-volatile memory (NVM) systems, and 2D and 3D memory systems. We hope that this survey will help the researchers in gaining insight into the potential role of compression approach in memory components of future extreme-scale systems.

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Section: Factors and Tradeoffs In Compressionmentioning

confidence: 99%

“…Choi et al [31] propose an adaptive compression technique for NVM cache which carefully controls additional writes due to compression. Their technique tracks the miss-rate of the compressed and uncompressed blocks by using set-sampling to determine whether cache compression is beneficial.…”

Section: Techniques For Non-volatile Memoriesmentioning

confidence: 99%

A Survey Of Architectural Approaches for Data Compression in Cache and Main Memory Systems

Mittal

Vetter

2016

IEEE Trans. Parallel Distrib. Syst.

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“…Finally, the possibility of storing compressed blocks in NV-LLCs has hardly been explored and anyway it has never been proposed to extend lifetime. For example, Choi et al explores an adaptation of the DCC compression scheme proposed for SRAM caches [34], but applying it to embedded NVM caches [35]. Just as with the DCC scheme for conventional caches, the aim is to increase the effective capacity by allowing the total number of compressed blocks stored in a cache set to exceed the nominal associativity.…”

Section: L2c2: Last-level Compressed-contents Nv Cachementioning

confidence: 99%

L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime

et al. 2023

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Several emerging non-volatile (NV) memory technologies are rising as interesting alternatives to build the Last-Level Cache (LLC). Their advantages, compared to SRAM memory, are higher density and lower static power, but write operations wear out the bitcells to the point of eventually losing their storage capacity. In this context, this paper presents a novel LLC organization designed to extend the lifetime of the NV data array and a procedure to forecast in detail the capacity and performance of such an NV-LLC over its lifetime. From a methodological point of view, although different approaches are used in the literature to analyze the degradation of an NV-LLC, none of them allows to study in detail its temporal evolution. In this sense, this work proposes a forecasting procedure that combines detailed simulation and prediction, allowing an accurate analysis of the impact of different cache control policies and mechanisms (replacement, wear-leveling, compression, etc.) on the temporal evolution of the indices of interest, such as the effective capacity of the NV-LLC or the system IPC. We also introduce L2C2, a LLC design intended for implementation in NV memory technology that combines fault tolerance, compression, and internal write wear leveling for the first time. Compression is not used to store more blocks and increase the hit rate, but to reduce the write rate and increase the lifetime during which the cache supports near-peak performance. In addition, to support byte loss without performance drop, L2C2 inherently allows N redundant bytes to be added to each cache entry. Thus, L2C2+N, the endurance-scaled version of L2C2, allows balancing the cost of redundant capacity with the benefit of longer lifetime. For instance, as a use case, we have implemented the L2C2 cache with STT-RAM technology. It has affordable hardware overheads compared to that of a baseline NV-LLC without compression in terms of area, latency and energy consumption, and increases up to 6-37 times the time in which 50% of the effective capacity is degraded, depending on the variability in the manufacturing process. Compared to L2C2, L2C2+6 which adds 6 bytes of redundant capacity per entry, that means 9.1% of storage overhead, can increase up to 1.4-4.3 times the time in which the system gets its initial peak performance degraded.

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“…Data compression reduces the block size. This is beneficial in the NVM context because it allows fewer bits to be written and consequently extends the lifetime of the main memory or cache [7], [9], [17], [27]. Yet, compression has another benefit in the context of a byte-level fault tolerant NV cache such as L2C2: it allows cache frames with dead bytes to hold blocks if compression is high enough [12], [17].…”

Section: B Data Compressionmentioning

confidence: 99%

“…To cope with these cases, we can stop the prediction, so ending the epoch and starting a new simulation. Alternatively, we can continue the prediction, also allowing some more error and apply the previous value wb f rame (7). In this work, we will adopt this second approach.…”

Section: A Approximate Forecasting Procedures With Frame-disablingmentioning

confidence: 99%

L2C2: Last-Level Compressed-Cache NVM and a Procedure to Forecast Performance and Lifetime

Escuin¹,

Ibáñez²,

Monreal³

et al. 2022

Preprint

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Adaptive cache compression for non-volatile memories in embedded system

Cited by 6 publications

References 19 publications

A Survey Of Architectural Approaches for Data Compression in Cache and Main Memory Systems

A Survey Of Architectural Approaches for Data Compression in Cache and Main Memory Systems

L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime

L2C2: Last-Level Compressed-Cache NVM and a Procedure to Forecast Performance and Lifetime

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