Adaptive ECC for Tailored Protection of Nanoscale Memory

Shin, Dongyeob; Park, Jongsun; Park, Jangwon; Sauseng, Paul; Bhunia, Swarup

doi:10.1109/mdat.2016.2615844

Cited by 9 publications

(11 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Similar studies have been conducted for FPGAs [8]. In a study on reduced voltage Block RAM in an FPGA, it was demonstrated that all errors can be detected and corrected using Error-Correction-Codes, while saving 60% of the energy [1], [9]. However, errors in logic fabric, e.g., Look-Up-Tables and DSP units, are difficult to tackle, while being the largest energy sink [8], [10].…”

Section: Introductionmentioning

confidence: 66%

See 1 more Smart Citation

A High-Level Approach for Energy Efficiency Improvement of FPGAs by Voltage Trimming

Safarpour¹

2021

Preprint

View full text Add to dashboard Cite

show abstract

Section: Introductionmentioning

confidence: 66%

“…We employed ABFT as the error detection mechanism for the memory instead of ECCs [9], adjusting the operating voltage and frequency based on error detection. The row checksum was added to the matrices before committing them into the BRAM; then the BRAM voltage was reduced from the default 1V towards 0.5V.…”

Section: B Voltage Reductions Of Bramsmentioning

confidence: 99%

A High-Level Approach for Energy Efficiency Improvement of FPGAs by Voltage Trimming

Safarpour¹

2021

Preprint

View full text Add to dashboard Cite

show abstract

“…Recently, specifications of error-correction capabilities and the data lengths are increasingly diversified, and it is necessary for making BCH decoders be flexible to cope with the increased requirements of reconfigurability. Targeting the multi-standard solutions, only few studies have been reported for sharing the processing elements in multi-t BCH decoders, which can change their correcting conditions within only the same GF dimension m [18]- [20]. For the sake of simplicity, therefore, we denote this multi-t fixed-m BCH decoder as the partially-flexible BCH decoder.…”

Section: Introductionmentioning

confidence: 99%

Area-Optimized Fully-Flexible BCH Decoder for Multiple GF Dimensions

Park

Lee

2018

IEEE Access

Self Cite

View full text Add to dashboard Cite

Recently, there are increasing demands for fully flexible Bose-Chaudhuri-Hocquenghem (BCH) decoders, which can support different dimensions of Galois fields (GF) operations. As the previous BCH decoders are mainly targeting the fixed GF operations, the conventional techniques are no longer suitable for multiple GF dimensions. For the area-optimized flexible BCH decoders, in this paper, we present several optimization schemes for reducing hardware costs of multi-dimensional GF operations. In the proposed optimizations, we first reformulate the matrix operations in syndrome calculation and Chien search for sharing more common sub-expressions between GF operations having different dimensions. The cellbased multi-m GF multiplier is newly introduced for the area-efficient flexible key-equation solver. As case studies, we design several prototype flexible BCH decoders for digital video broadcasting systems and NAND flash memory controllers managing different page sizes. The implementation results show that the proposed fully-flexible BCH decoder architecture remarkably enhances the area-efficiency compared with the conventional solutions.INDEX TERMS Bose-Chaudhuri-Hocquenghem (BCH) decoder, Galois-field (GF) arithmetic, optimization, low complexity, VLSI design.

show abstract

“…Although this system is adaptable and hardware-implemented, the reconfiguration is not triggered by changes detected by the system; instead, they are pre-scheduled. In Reference [41], Shin et al propose an adaptive ECC with three correction capabilities (1-, 2-and 4-errors) that adapts depending on the error frequency, which is analyzed in the control unit. Similarly, Silva et al present in [42] CLC-adaptive, a column line code-based ECC able to activate CLC-Extended decoder depending on the result of initial CLC-standard decoding.…”

mentioning

confidence: 99%

“…Reference [41] studies whether scrubbing is really necessary for cache memories. Considering the cache size and the FIT (failure in time), the authors calculate the DUE (detected unrecoverable errors) rate, and they assert that scrubbing is necessary only in very large (from hundreds of megabytes) caches.…”

mentioning

confidence: 99%

Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM

et al. 2020

View full text Add to dashboard Cite

Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive fault tolerance mechanism based on error correction codes (ECC), able to modify its behavior when the error conditions change without increasing the redundancy. As a case example, we have designed a mechanism that can detect intermittent faults and swap from an initial generic ECC to a specific ECC capable of tolerating one intermittent fault. We have inserted the mechanism in the memory system of a 32-bit RISC processor and validated it by using VHDL simulation-based fault injection. We have used two (39, 32) codes: a single error correction–double error detection (SEC–DED) and a code developed by our research group, called EPB3932, capable of correcting single errors and double and triple adjacent errors that include a bit previously tagged as error-prone. The results of injecting transient, intermittent, and combinations of intermittent and transient faults show that the proposed mechanism works properly. As an example, the percentage of failures and latent errors is 0% when injecting a triple adjacent fault after an intermittent stuck-at fault. We have synthesized the adaptive fault tolerance mechanism proposed in two types of FPGAs: non-reconfigurable and partially reconfigurable. In both cases, the overhead introduced is affordable in terms of hardware, time and power consumption.

show abstract

Adaptive ECC for Tailored Protection of Nanoscale Memory

Cited by 9 publications

References 11 publications

A High-Level Approach for Energy Efficiency Improvement of FPGAs by Voltage Trimming

A High-Level Approach for Energy Efficiency Improvement of FPGAs by Voltage Trimming

Area-Optimized Fully-Flexible BCH Decoder for Multiple GF Dimensions

Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM

Contact Info

Product

Resources

About