Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures

Kodi,; Sarathy,; Louri,; Wang, Hong

doi:10.1109/aspdac.2009.4796432

Cited by 13 publications

(8 citation statements)

References 23 publications

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“…Therefore, NBTI (repeaters) and electromigration (copper interconnects) are the two primary aging problems associated with NoC links. Unfortunately, previous works on NoCs have completely ignored the role of links in their reliability analysis, focusing solely on the routers [10,6]. We demonstrate that such limitations can grossly underestimate the NoC lifetime by nearly a factor of 2.…”

Section: Introductionmentioning

confidence: 92%

Towards graceful aging degradation in NoCs through an adaptive routing algorithm

Bhardwaj

Chakraborty

Roy

2012

Proceedings of the 49th Annual Design Automation Conference

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Continuous technology scaling has made aging mechanisms such as Negative Bias Temperature Instability (NBTI) and electromigration primary concerns in Network-on-Chip (NoC) designs. In this paper, we model the effects of these aging mechanisms on NoC components such as routers and links using a novel reliability metric called Traffic Threshold per Epoch (TTpE). We observe a critical need of a robust aging-aware routing algorithm that not only reduces power-performance overheads caused due to aging degradation but also minimizes the stress experienced by heavily utilized routers and links. To solve this problem, we propose an aging-aware adaptive routing algorithm and a router microarchitecture that routes the packets along the paths which are both least congested and experience minimum aging stress. After an extensive experimental analysis using real workloads, we observe a 13%, 12.7% average overhead reduction in network latency and EnergyDelay-Product-Per-Flit (EDPPF) and a 10.4% improvement in performance using our aging-aware routing algorithm.

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Section: Introductionmentioning

confidence: 92%

Towards graceful aging degradation in NoCs through an adaptive routing algorithm

Bhardwaj

Chakraborty

Roy

2012

Proceedings of the 49th Annual Design Automation Conference

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“…Kodi et al [68] on the other hand, introduced a dualfunction links architecture called iDeal which unlike input buffers, does not consume a lot of power. iDeal uses a dynamic router buffer allocation to allocate incoming flits to any available buffer.…”

Section: Reducing Power Consumption In the Noc Router Architecturementioning

confidence: 99%

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

Ofori-Attah¹,

Wang²,

Agyeman³

2018

EAI Endorsed Transactions on Industrial Networks and Intelligen

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Power consumption in Complementary Metal Oxide Semiconductor (CMOS) technology has escalated to a point that only a fractional part of many-core chips can be powered-on at a time. Fortunately, this fraction can be increased at the expense of performance through the dark-silicon solution. However, with manycore integration set to be heading towards its thousands, power consumption and temperature increases per time, meaning the number of active nodes must be reduced drastically. Therefore, optimized techniques are demanded for continuous advancement in technology. Existing efforts try to overcome this challenge by activating nodes from different parts of the chip at the expense of communication latency. Other efforts on the other hand employ run-time power management techniques to manage the power performance of the cores trading-off performance for power. We found out that, for a significant amount of power to saved and high temperature to be avoided, focus should be on reducing the power consumption of all the on-chip components. Especially, the memory hierarchy and the interconnect. Power consumption can be minimized by, reducing the size of high leakage power dissipating elements, turning-off idle resources and integrating power saving materials.

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“…Instead of the removing all of the buffers in the NoC, the following proposed techniques displace all of the buffers in the router and utilize them in other areas of the NoC to house packets. For example, Kodi et al [78] proposed iDeal. In this architecture, dual function links are employed.…”

Section: Input Buffer Alternativesmentioning

confidence: 99%

Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer

Ofori-Attah

Bhebhe

Agyeman

2017

JLPEA

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The disparity between memory and CPU have been ameliorated by the introduction of Network-on-Chip-based Chip-Multiprocessors (NoC-based CMPS). However, power consumption continues to be an aggressive stumbling block halting the progress of technology. Miniaturized transistors invoke many-core integration at the cost of high power consumption caused by the components in NoC-based CMPs; particularly caches and routers. If NoC-based CMPs are to be standardised as the future of technology design, it is imperative that the power demands of its components are optimized. Much research effort has been put into finding techniques that can improve the power efficiency for both cache and router architectures. This work presents a survey of power-saving techniques for efficient NoC designs with a focus on the cache and router components, such as the buffer and crossbar. Nonetheless, the aim of this work is to compile a quick reference guide of power-saving techniques for engineers and researchers.

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Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures

Cited by 13 publications

References 23 publications

Towards graceful aging degradation in NoCs through an adaptive routing algorithm

Towards graceful aging degradation in NoCs through an adaptive routing algorithm

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer

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