Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer

Ofori-Attah, Emmanuel; Bhebhe, Washington; Agyeman, Michael Opoku

doi:10.3390/jlpea7020014

Cited by 12 publications

(8 citation statements)

References 89 publications

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“…Other than that blocks are transferred to a new inactive mode. This is a well-known concept in caches called the migration principle to save the power consumption [23,24]. [25].…”

Section: Figure 2: Control Unitmentioning

confidence: 99%

Dual-Port Content Addressable Memory for Cache Memory Applications

Abumwais¹,

Amirjanov²,

Uyar³

et al. 2022

Computers, Materials &Amp; Continua

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Multicore systems oftentimes use multiple levels of cache to bridge the gap between processor and memory speed. This paper presents a new design of a dedicated pipeline cache memory for multicore processors called dual port content addressable memory (DPCAM). In addition, it proposes a new replacement algorithm based on hardware which is called a near-far access replacement algorithm (NFRA) to reduce the cost overhead of the cache controller and improve the cache access latency. The experimental results indicated that the latency for write and read operations are significantly less in comparison with a set-associative cache memory. Moreover, it was shown that a latency of a read operation is nearly constant regardless of the size of DPCAM. However, an estimation of the power dissipation showed that DPCAM consumes about 7% greater than a set-associative cache memory of the same size. These results encourage for embedding DPCAM within the multicore processors as a small shared cache memory.

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“…Other than that blocks are transferred to a new inactive mode. This is a well-known concept in caches called the migration principle to save the power consumption [23,24]. [25].…”

Section: Figure 2: Control Unitmentioning

confidence: 99%

Dual-Port Content Addressable Memory for Cache Memory Applications

Abumwais¹,

Amirjanov²,

Uyar³

et al. 2022

Computers, Materials &Amp; Continua

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“…In routers buffers are the main source of power dissipation. So an alternative was put forward in the form of bufferless routers [41]. In a router without buffers, flow control deflection algorithms are used, where in packets have to be transmitted on their arrival only.…”

Section: 32mentioning

confidence: 99%

A Review of Design Approaches for Enhancing the Performance of NoCs at Communication Centric Level

Manzoor

Mir

Hakim

2021

SCPE

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As the trend of technology shrinking continues a vast amount of processors are being incorporated in a limited space. Due to this almost half of the chip area in Multi-Processor Systems-on-Chips (MPSoCs) is under interconnections, which pose a big problem for communication. Network-on-Chips (NoCs) evolved as a significant scalable solution for removing wiring congestion and communication problem in MPSoCs. NoCs provide the advantage of customized architecture, increased scalability and bandwidth. NoC is a structured framework where communication is the prime concern. In this review paper we present an overview of research and design approaches in the communication centric areas of NoCs. Here we have tried to discuss and iterate most of the available work done for communication in 2D NoCs. This paper gives the insight of different attributes and performance parameters of NoCs. Further it gives a detailed description of how topology, flow control and routing mechanisms can affect the qualitative aspects (performance) of NoCs. It then explains how various attributes of routing can help in increasing the efficacy of NoCs. Subsequently a brief review of different simulators used for NoCs is given. All of this is provided based on the survey of academic, theoretical and experimental approaches presented in the past. Finally some suggestions for future work are also given.

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“…On-chip cache memories account for a significant portion [70][71][72][73][74][75][76][77] of power consumption in embedded devices. Therefore, for mobile devices that run on batteries, efficient power optimization techniques are highly in demand as the sizes of transistors progressively decreases.…”

Section: Reducing Power Consumption In the Cache Architecturementioning

confidence: 99%

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

Ofori-Attah¹,

Wang²,

Agyeman³

2018

EAI Endorsed Transactions on Industrial Networks and Intelligen

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Power consumption in Complementary Metal Oxide Semiconductor (CMOS) technology has escalated to a point that only a fractional part of many-core chips can be powered-on at a time. Fortunately, this fraction can be increased at the expense of performance through the dark-silicon solution. However, with manycore integration set to be heading towards its thousands, power consumption and temperature increases per time, meaning the number of active nodes must be reduced drastically. Therefore, optimized techniques are demanded for continuous advancement in technology. Existing efforts try to overcome this challenge by activating nodes from different parts of the chip at the expense of communication latency. Other efforts on the other hand employ run-time power management techniques to manage the power performance of the cores trading-off performance for power. We found out that, for a significant amount of power to saved and high temperature to be avoided, focus should be on reducing the power consumption of all the on-chip components. Especially, the memory hierarchy and the interconnect. Power consumption can be minimized by, reducing the size of high leakage power dissipating elements, turning-off idle resources and integrating power saving materials.

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Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer

Cited by 12 publications

References 89 publications

Dual-Port Content Addressable Memory for Cache Memory Applications

Dual-Port Content Addressable Memory for Cache Memory Applications

A Review of Design Approaches for Enhancing the Performance of NoCs at Communication Centric Level

A Survey of System Level Power Management Schemes in the Dark-Silicon Era for Many-Core Architectures

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