Towards graceful aging degradation in NoCs through an adaptive routing algorithm

Bhardwaj, Kshitij; Chakraborty, Koushik; Roy, Sanghamitra

doi:10.1145/2228360.2228429

Cited by 30 publications

(10 citation statements)

References 18 publications

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“…While there has been a wide scope of studies tackling different reliability issues (NBTI, TDDB, HCI) in processing elements [11,21], there is only a limited number of works which address wear-out mitigation in the on-chip communication infrastructure of such systems. Bhardwaj et al implemented a dynamic routing algorithm to equalize NBTI and electromigration aging across the on-chip network [3]. [20].…”

Section: Related Workmentioning

confidence: 99%

“…Various aging mechanisms such as Negative Bias Temperature Instability (NBTI), Hot Carrier Injection (HCI), Time Dependent Dielectric Breakdown (TDDB), and Electromigration play a major role in degrading performance characteristics of NoCs over time. Such a performance degradation can have a massive system level impact in NoCs, and may ultimately shorten the chip lifetime prematurely [2,3].…”

Section: Introductionmentioning

confidence: 99%

“…For example, Fu et al propose techniques to mitigate NBTI aging in NoCs by balancing the duty cycle in the Virtual Allocator circuits [10]. Bhardwaj et al propose aging-aware adaptive routing to throttle NBTI and Electromigration degradation [3]. NBTI is a critical but recoverable device aging mechanism.…”

Section: Introductionmentioning

confidence: 99%

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HCI-tolerant NoC router microarchitecture

Ancajas

Nickerson

Chakraborty

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

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The trend towards massive parallel computing has necessitated the need for an On-Chip communication framework that can scale well with the increasing number of cores. At the same time, technology scaling has made transistors susceptible to a multitude of reliability issues (NBTI, HCI, TDDB). In this work, we propose an HCI-Tolerant microarchitecture for an NoC Router by manipulating the switching activity around the circuit. We find that most of the switching activity (the primary cause of HCI degradation) are only concentrated in a few parts of the circuit, severely degrading some portions more than others. Our techniques increase the lifetime of an NoC router by balancing this switching activity. Compared to an NoC without any reliability techniques, our best schemes improve the switching activity distribution, clock cycle degradation, system performance and energy delay product per flit by 19%, 26%, 11% and 17%, respectively, on an average.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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HCI-tolerant NoC router microarchitecture

Ancajas

Nickerson

Chakraborty

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

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“…Bhardwaj et al [6,5] propose routing algorithms to mitigate multiple aging mechanisms. They also point out that NBTI plays a major role in NoC router aging, and their routing techniques balance the traffic load across the network to level-out the aging rates among the routers.…”

Section: Related Workmentioning

confidence: 99%

“…Prior work has proposed various fault-tolerant routing algorithms and fault-insensitive router and link designs in an attempt to manage faults as they occur [38,32,12,6,5,11], however, network isolation and key resource partitioning cannot be fully resolved using only such reactive techniques. Ideally, one would prefer to develop proactive mechanisms to extend the healthy status of the system without failure, rather than react to the faults once they occur.…”

Section: Introductionmentioning

confidence: 99%

Use it or lose it

Vitkovskiy

Gratz

Soteriou

2013

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture

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Moore's Law scaling is continuing to yield even higher transistor density with each succeeding process generation, leading to today's multi-core Chip Multi-Processors (CMPs) with tens or even hundreds of interconnected cores or tiles. Unfortunately, deep sub-micron CMOS process technology is marred by increasing susceptibility to wearout. Prolonged operational stress gives rise to accelerated wearout and failure, due to several physical failure mechanisms, including Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI). Each failure mechanism correlates with different usage-based stresses, all of which can eventually generate permanent faults. While the wearout of an individual core in many-core CMPs may not necessarily be catastrophic for the system, a single fault in the interprocessor Network-on-Chip (NoC) fabric could render the entire chip useless, as it could lead to protocol-level deadlocks, or even partition away vital components such as the memory controller or other critical I/O. In this paper, we develop critical path models for HCI-and NBTI-induced wear due to the actual stresses caused by real workloads, applied onto the interconnect microarchitecture. A key finding from this modeling being that, counter to prevailing wisdom, wearout in the CMP on-chip interconnect is correlated with lack of load observed in the NoC routers, rather than high load. We then develop a novel wearout-decelerating scheme in which routers under low load have their wearout-sensitive components exercised, without significantly impacting cycle time, pipeline depth, area or power consumption of the overall router. We subsequently show that the proposed design yields a 13.8×-65× increase in CMP lifetime.

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Dynamic Programming-Based Lifetime Reliability Optimization in Networks-on-Chip

Wang

Mak

2015

VLSI-SoC: Internet of Things Foundations

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International audienceTechnology scaling leads to the reliability issue as a primary concern in Networks-on-Chip (NoC) design. Due to routing algorithms, some routers may age much faster than others, which become a bottleneck for system lifetime. In this chapter, lifetime is modeled as a resource consumed over time. A metric lifetime budget is associated with each router, indicating the maximum allowed workload for current period. Since the heterogeneity in router lifetime reliability has strong correlation with the routing algorithm, we define a problem to optimize the lifetime by routing packets along the path with maximum lifetime budgets. A dynamic programming-based lifetime-aware routing algorithm is proposed to optimize the lifetime distribution of routers. The dynamic programming network approach is employed to solve this problem with linear complexity. The experimental results show that the lifetime-aware routing has around 20 %, 45 %, 55 % minimal MTTF improvement than XY routing, NoP routing, and Oddeven routing, respectively

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Towards graceful aging degradation in NoCs through an adaptive routing algorithm

Cited by 30 publications

References 18 publications

HCI-tolerant NoC router microarchitecture

HCI-tolerant NoC router microarchitecture

Use it or lose it

Dynamic Programming-Based Lifetime Reliability Optimization in Networks-on-Chip

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