Adaptive motion estimator for the H264 coder

Abstract

In this paper we propose an adaptive motion estimation circuit that can be dynamically reconfigured by the best algorithm based on the video nature of the application under running. This configuration is based on a recognition step that collects the motion information's of each block from its same block in the previous images and their neighbour's blocs in the current image. The proposed circuit has been designed at Register Transfer Level (RTL) level by using the VHDL language and can be configured by three algorithms (Full search, Spiral search with threshold and Spiral search without threshold). After being integrated into a H264 Codec, experimental results show that the adaptive motion estimator allows better results in term of Peak Signal to Noise Ratio (PSNR) and compression ratio relatively to the static based estimators.

A Model-Driven Platform for Dynamic Partially Reconfigurable Architectures: A Case Study of a Watermarking System

“…The resource usage of the whole system was compared to three static versions of the system: a static version implementing only the GS algorithm, a static version implementing only the 4SS algorithm, and a third version using adaptive motion estimation proposed in our previous work [ 26 ]. The difference between the third version and the one used in the current paper is that it did not use dynamic partial reconfiguration.…”

“…The difference between the third version and the one used in the current paper is that it did not use dynamic partial reconfiguration. The estimator in [ 26 ] contained hardware modules implementing both the GS and the 4SS algorithms present at the same time on the chip, but only one of these algorithms was active at a given time depending on the motion speed. Despite its adaptivity to motion speed compared to an estimator implementing only one algorithm, this solution has a non-negligible resource usage overhead as shown in Table 2 .…”

“…Despite its adaptivity to motion speed compared to an estimator implementing only one algorithm, this solution has a non-negligible resource usage overhead as shown in Table 2 . The resource usage of the dynamic partially reconfigurable architecture is significantly lower than the one used in [ 26 ] since only one algorithm is present on the board at a given time. If we compare the resource usage of the DPR version with the static versions implementing only one estimation algorithm, we notice that DPR implies a slight resource usage increase, which is due to the additional hardware modules needed for reconfiguration (reconfiguration decision-making and reconfiguration interface).…”

“…The average power consumption of the reconfigurable watermarking system while processing the three video sequences was 140 mW. The same video sequences were executed in the non-DPR version of the watermarking system using the adaptive motion estimator proposed in [ 26 ]. The average power consumption of the system was 214 mW, which shows that the DPR version allowed a power consumption reduction of 34.57%.…”

“…To determine the requirements imposed by a video watermarking application and architecture, we carried out a study to extract the PSNR [ 25 ] values expected in video watermarking applications. The power consumption and frequency constraint were defined regarding a previous implementation using the motion estimator module proposed in [ 26 ]. This implementation was an adaptive non-DPR (non-Partial Dynamic Reconfiguration) one.…”