Adaptive Packet Relocator in Wireless Network-on-Chip (WiNoC)

Rusli, Mohd Shahrizal; Lit, Asrani; Marsono, Muhammad Nadzir; Palesi, Maurizio

doi:10.1007/978-981-10-6502-6_61

Cited by 3 publications

(1 citation statement)

References 22 publications

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“…Hence, this explains how topology impacts the network latency. Meanwhile, as data traversing process dissipates energy these hop counts indirectly affects network energy consumption [27][28][29].…”

Section: Wireless Noc Architecturementioning

confidence: 99%

Comparative performance evaluation of routing algorithm and topology size for wireless network-on-chip

2019

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Wireless Network-on-Chip or WiNoC is an alternative to traditional planar on-chip networks. On-chip wireless links are utilized to reduce latency between distant nodes due to its capability to communicate with far-away node within a single hop. This paper analyzes the impact of various routing schemes and the effect of WiNoC sizes on network traffic distributions compared to conventional mesh NoC. Radio hubs (4×4) are evenly placed on WiNoC to analyze global average delay, throughput, energy consumption and wireless utilization. For validation, three various network sizes (8×8, 16×16 and 32×32) of mesh NoC and WiNoC architectures are simulated on cycle-accurate Noxim simulator under numerous traffic load distributions. Simulation results show that WiNoC architecture with the 16×16 network size has better average speedup (∼1.2×) and improved network throughputs by 6.36% in non-uniform transpose traffic distribution. As the trade-off, WiNoC requires 63% higher energy consumption compared to the classical wired NoC mesh.

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Section: Wireless Noc Architecturementioning

confidence: 99%

Comparative performance evaluation of routing algorithm and topology size for wireless network-on-chip

2019

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WiZ-BMS: A Hybrid Wireless Network-on-Chip Design with Fully Adaptive Routing

Rahaman

Ghosal

Giri

2022

2022 IEEE International Symposium on Smart Electronic Systems (iSES)

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Novel Bi-UWB on-Chip Antenna for Wireless NoC

Gaha

Balti

2022

Micromachines

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Communication between on-chip cores is a challenging issue for high-performance network-on-chip (NoC)design. Wireless NoC (WiNoC) represents an alternative design for planar wired interconnects, aiming to reduce latency and improve bandwidth. In this paper, a novel on-chip fractal antenna is designed and characterized. In order to disseminate interference affecting NoC performance in order to enhance on-chip quality of service (QoS), a set of exclusive sub-channels are assigned to each antenna. The proposed antenna has two wide bands (bi-WB)—B1 and B2, of (63–78) GHz and (101–157) GHz, respectively. The multi-band antenna allows different channel allocations for on-chip core communications. This WiNoC design exhibits improved performance, due to its enhanced antenna bandwidth and the benefit provided by the developed algorithm that can scan and compare to assign the best (upload or download) sub-channels to each antenna.

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Adaptive Packet Relocator in Wireless Network-on-Chip (WiNoC)

Cited by 3 publications

References 22 publications

Comparative performance evaluation of routing algorithm and topology size for wireless network-on-chip

Comparative performance evaluation of routing algorithm and topology size for wireless network-on-chip

WiZ-BMS: A Hybrid Wireless Network-on-Chip Design with Fully Adaptive Routing

Novel Bi-UWB on-Chip Antenna for Wireless NoC

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