Address-Event Communication Using Token-Ring Mutual Exclusion

Imam, Nabil; Manohar, Rajit

doi:10.1109/async.2011.20

Cited by 17 publications

(14 citation statements)

References 16 publications

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“…1(b)). Communication at the input and output of the core uses an address-event representation (AER), which encodes binary activity, such as A(t), by sending the locations of active elements via a multiplexed channel [10]. In order to minimize active power consumption, we perform neural updates in an event-driven manner.…”

Section: Methodsmentioning

confidence: 99%

Building block of a programmable neuromorphic substrate: A digital neurosynaptic core

Arthur

Merolla

Akopyan

et al. 2012

The 2012 International Joint Conference on Neural Networks (IJCNN)

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111

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Abstract-The grand challenge of neuromorphic computation is to develop a flexible brain-like architecture capable of a wide array of real-time applications, while striving towards the ultra-low power consumption and compact size of biological neural systems. To this end, we fabricated a key building block of a modular neuromorphic architecture, a neurosynaptic core. Our implementation consists of 256 integrate-and-fire neurons and a 1,024×256 SRAM crossbar memory for synapses that fits in 4.2mm 2 using a 45nm SOI process and consumes just 45pJ per spike. The core is fully configurable in terms of neuron parameters, axon types, and synapse states and its fully digital implementation achieves one-to-one correspondence with software simulation models. One-to-one correspondence allows us to introduce an abstract neural programming model for our chip, a contract guaranteeing that any application developed in software functions identically in hardware. This contract allows us to rapidly test and map applications from control, machine vision, and classification. To demonstrate, we present four test cases (i) a robot driving in a virtual environment, (ii) the classic game of pong, (iii) visual digit recognition and (iv) an autoassociative memory.

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Section: Methodsmentioning

confidence: 99%

Building block of a programmable neuromorphic substrate: A digital neurosynaptic core

Arthur

Merolla

Akopyan

et al. 2012

The 2012 International Joint Conference on Neural Networks (IJCNN)

Self Cite

111

View full text Add to dashboard Cite

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“…Each of the patterns can be used in distinct computations, as described in the caption. Our neuron reproduces all the prominent spiking patterns seen in biological neurons [4]. Many of them can be generated through a (9,7) fixedpoint twos complement number representation (i.e.…”

Section: Resultsmentioning

confidence: 99%

“…Communication in neuromorphic systems is discretized into address-event representation (AER) packets [4], which encode information about neuron spiking activity. The minimal packet is a (source, destination, timestamp) tuple indicating the source, destination, and time of a spike.…”

Section: Neuromorphic System Architecturementioning

confidence: 99%

“…To implement the full range of spatiotemporal codes used in biological neural systems, neuromorphic hardware designs need to incorporate neuron models that reproduce the variety of spiking patterns of real neurons [3], and routing circuits that transmit information about the time and place of spikes across the system [4,5]. In practice, neuromorphic systems can be reconfigured to execute different algorithms by adjusting the dynamical properties of neurons (through configurable model parameters) and by changing the connectivity of the network (through configurable routing).…”

Section: Introductionmentioning

confidence: 99%

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Neural spiking dynamics in asynchronous digital circuits

Imam

Wecker

Tse

et al. 2013

The 2013 International Joint Conference on Neural Networks (IJCNN)

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Abstract-We implement a digital neuron in silicon using delay-insensitive asynchronous circuits. Our design numerically solves the Izhikevich equations with a fixed-point number representation, resulting in a compact and energy-efficient neuron with a variety of dynamical characteristics. A digital implementation results in stable, reliable and highly programmable circuits, while an asynchronous design style leads to energy-efficient clockless neurons and their networks that mimic the event-driven nature of biological nervous systems. In 65 nm CMOS technology at 1 V operating voltage and a 16-bit word length, our neuron can update its state 11,600 times per millisecond while consuming 0.5 nJ per update. The design occupies 29,500 µm 2 and can be used to construct dense neuromorphic systems. Our neuron exhibits the full repertoire of spiking features seen in biological neurons, resulting in a range of computational properties that can be used in artificial systems running neural-inspired algorithms, in neural prosthetic devices, and in accelerated brain simulations.

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“…On the output side, an AER transmitter [8] encodes spiking activity by sending the locations of active neurons through a multiplexed channel, leveraging the fact that the bandwidth of wires (easily larger than 100s of MHz) is orders of magnitude larger than the bandwidth of biological axons (in the 10's of Hz range). The spikes can be sent off chip, or routed to an axon of another core via a look-up table.…”

Section: B Communication Infrastructurementioning

confidence: 99%

A Digital Neurosynaptic Core Using Event-Driven QDI Circuits

Imam

Akopyan

Arthur

et al. 2012

2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems

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Abstract-We design and implement a key building block of a scalable neuromorphic architecture capable of running spiking neural networks in compact and low-power hardware. Our innovation is a configurable neurosynaptic core that combines 256 integrate-and-fire neurons, 1024 input axons, and 1024x256 synapses in 4.2mm 2 of silicon using a 45nm SOI process. We are able to achieve ultra-low energy consumption 1) at the circuit-level by using an asynchronous design where circuits only switch while performing neural updates; 2) at the core-level by implementing a 256 neural fanout in a single operation using a crossbar memory; and 3) at the architecturelevel by restricting core-to-core communication to spike events, which occur relatively sparsely in time. Our implementation is purely digital, resulting in reliable and deterministic operation that achieves for the first time one-to-one correspondence with a software simulator. At 45pJ per spike, our core is readily scalable and provides a platform for implementing a wide array of real-time computations. As an example, we demonstrate a sound localization system using coincidence-detecting neurons.

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Address-Event Communication Using Token-Ring Mutual Exclusion

Cited by 17 publications

References 16 publications

Building block of a programmable neuromorphic substrate: A digital neurosynaptic core

Building block of a programmable neuromorphic substrate: A digital neurosynaptic core

Neural spiking dynamics in asynchronous digital circuits

A Digital Neurosynaptic Core Using Event-Driven QDI Circuits

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