Address Translation Optimization for Unified Parallel C Multi-dimensional Arrays

Abstract

Partitioned Global Address Space (PGAS) languages offer significant programmability advantages with its global memory view abstraction, one-sided communication constructs and data locality awareness. These attributes place PGAS languages at the forefront of possible solutions to the exploding programming complexity in the many-core architectures. To enable the shared address space abstraction, PGAS languages use an address translation mechanism while accessing shared memory to convert shared addresses to physical addresses. This mechanism is already expensive in terms of performance in distributed memory environments, but it becomes a major bottleneck in machines with shared memory support where the access latencies are significantly lower. Multi-and manycore processors exhibit even lower latencies for shared data due to on-chip cache space utilization. Thus, efficient handling of address translation becomes even more crucial as this overhead may easily become the dominant factor in the overall data access time for such architectures. To alleviate address translation overhead, this paper introduces a new mechanism targeting multi-dimensional arrays used in most scientific and image processing applications. Relative costs and the implementation details for UPC are evaluated with different workloads (matrix multiplication, Random Access benchmark and Sobel edge detection) on two different platforms: a manycore system, the TILE64 (a 64 core processor) and a dualsocket, quad-core Intel Nehalem system (up to 16 threads). Our optimization provides substantial performance improvements, up to 40x. In addition, the proposed mechanism can easily be integrated into compilers abstracting it from the programmers. Accordingly, this improves UPC productivity as it will reduce manual optimization efforts required to minimize the address translation overhead.

Enabling PGAS Productivity with Hardware Support for Shared Address Mapping

“…They proposed a framework to assess the compilers and the runtime systems capabilities to optimize the overhead. Different compiler optimizations were researched, including optimization techniques such as lookup tables [Cantonnet et al 2005;Serres et al 2011a]; the reduced overhead is still significant, and the methods can consume a significant amount of memory. Alternative representations for shared pointers have also been implemented.…”

Hardware support for address mapping in PGAS languages

“…They proposed a framework to assess the compil-ers and the runtime systems capabilities to optimize such overheads. In order to solve those issues, different compiler optimizations have been researched including optimization techniques such as lookup tables: [5,18]; the reduced overhead is still significant and the methods can use a good amount of memory. Also, alternative representations for shared pointers have been implemented, for example phaseless pointers are used for shared addresses with a block size of 1 or infinity [8], this is only applicable to a few cases and still present a significant overheads.…”