2005 IEEE International SOI Conference Proceedings
DOI: 10.1109/soi.2005.1563594
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Advanced FinFET Technology: TiN Metal-gate CMOS and 3T/4T Device Integration

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Cited by 7 publications
(6 citation statements)
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“…Very recently, the conformal TiN deposition by a chemical vapor deposition (CVD) method has actively been developed for three-dimensional device structures in such a multigate MOSFET [29]- [32], and the well symmetrical of both nMOS and pMOS devices has been obtained without a channel doping, thanks to the midgap . However, to our knowledge, there have been no reports regarding TiN gate FinFETs using a conventional reactive sputtering, except our recent works [33], [34].…”
Section: Introductionmentioning
confidence: 93%
“…Very recently, the conformal TiN deposition by a chemical vapor deposition (CVD) method has actively been developed for three-dimensional device structures in such a multigate MOSFET [29]- [32], and the well symmetrical of both nMOS and pMOS devices has been obtained without a channel doping, thanks to the midgap . However, to our knowledge, there have been no reports regarding TiN gate FinFETs using a conventional reactive sputtering, except our recent works [33], [34].…”
Section: Introductionmentioning
confidence: 93%
“…As the starting material, we used lightly doped p-type (110)-oriented silicon-on-insulator (SOI) wafers to fabricate ideal rectangular cross-sectional Si-fin channels by orientation-dependent wet etching. [13][14][15][16] First, fin patterns were delineated parallel to the h112i direction by EB lithography and fin hard masks were formed by RIE, as shown in Figs. 1(b)- (2).…”
Section: Device Fabricationmentioning
confidence: 99%
“…[6][7][8][9][10][11][12] Very recently, the sputtered TiN gate has actively been applied in FinFETs because its midgap work function provides well symmetrical V th for FinFET CMOS without channel doping. [13][14][15][16] Moreover, it has been reported that the work function of sputtered TiN can be slightly adjusted by changing the nitrogen gas flow ratio R N ¼ N 2 =ðAr þ N 2 Þ during sputtering. 12,17) However, the R N dependences of the electrical characteristics of sputtered TiN gate bulk planar MOSFETs and FinFETs have not been investigated sufficiently.…”
Section: Introductionmentioning
confidence: 99%
“…[3][4][5][6][7][8][9][10][11] Very recently, the PVD-TiN gate has actively been developed for fin-type double-gate MOSFETs (FinFETs) because its midgap work function offers a symmetrical threshold voltage (V th ) for FinFET CMOS without channel doping. [12][13][14][15][16][17][18][19][20][21] One of the most important issues in PVD-TiN gate FinFET fabrication is PVD-TiN gate formation especially the PVD-TiN etching on the sidewalls of tall fin-channels by conventional reactive ion etching (RIE) owing to the low volatility of titanium (Ti) halogenides. 22,23) Since the effective channel width W eff in FinFETs is twice the fin height H fin , W eff ¼ 2H fin , a tall finchannel is very attractive for realizing a high drive current without increasing device area.…”
Section: Introductionmentioning
confidence: 99%