Advanced modeling of charge trapping: RTN, 1/f noise, SILC, and BTI

Goes, Wolfgang; Waltl, Michael; Wimmer, Yannick; Rzepa, G.

doi:10.1109/sispad.2014.6931567

Cited by 16 publications

(4 citation statements)

References 19 publications

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“…As a result, the activation energies of the two main traps in T2 are E a = 0.55 eV and E a = 0.68 eV, while in T4 the three traps feature E a = 0.68, 0.93, and 0.96 eV. Activation energies of border traps in the range 0.5-1 eV were already reported by other authors [36]- [38], [40] and attributed hole capturing to hydrogen bridges and E centers. Indeed, even if numerous paramagnetic centers have been observed in SiO 2 , the results of several density functional theory calculations indicate these defects to be very likely candidates for hole trapping in SiO 2 [37], [41].…”

Section: Time-dependent Defect Spectroscopysupporting

confidence: 67%

On Border Traps in Back-Side-Illuminated CMOS Image Sensor Oxides

Vici

Russo²,

Lovisi³

et al. 2020

IEEE Trans. Electron Devices

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CMOS image sensors (CISs) in back-sideilluminated configuration consist of photodiode arrays having metal lines and drive electronics beneath the active region with respect to the device/air interface so that the light reaches the photodiode active region directly. This enhances sensor quantum efficiency but reduces the electrical performance and reliability. The backside configuration is realized by flipping the wafer upside down, bonding it to a handling wafer, mechanically thinning it, and opening a through-silicon via with a long plasma etch. As a result, gate oxides in backside CISs show an increased density of donor-like border traps with respect to the conventional front-side-illuminated sensors. In this article, we try to add some information toward the comprehension of the origin and the electrical nature of those traps in backside gate oxides. To this aim, we performed negative bias temperature instability stress on p-channel MOSFETs during which the traps were filled by holes tunneling from the substrate and then studied the relaxation transients of the drain current after the stress was removed. The characteristic emission times of a few specific levels were obtained at different temperatures. This allowed us to extract values of the trap activation energies, which resulted coherent with hole-capturing E donor-like centers (trivalent silicon dangling bonds) commonly attributed to ionizing radiation. Index Terms-Backside illuminated (BSI) CMOS image sensors (CISs), gate oxide border traps, TDDS. I. INTRODUCTION A CMOS image sensor (CIS) is an array of light-sensitive pixels. Each pixel consists of a photo-diode (PD) and several control MOSFETs. In the front-side-illuminated (FSI) configuration [Fig. 1(a)], the light reaches the PD active region through the microlenses, the filters, the passivation layers, the metal lines, and the interdielectric layers [1], [2]. So, the Manuscript

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Section: Time-dependent Defect Spectroscopysupporting

confidence: 67%

On Border Traps in Back-Side-Illuminated CMOS Image Sensor Oxides

Vici

Russo²,

Lovisi³

et al. 2020

IEEE Trans. Electron Devices

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“…Then the modeling of oxide traps was performed based on our previously developed four-state non-radiative multiphonon (NMP) model [25]. This model has already been successfully applied to capture various aspects of charge trapping by oxide traps in Si technologies [54,65,66] and back-gated FETs with MoS 2 [40] and black phosphorus [33]. To simulate the hysteresis widths and offsets using the four-state NMP model, a set of microscopic defects was generated while assuming normally distributed model parameters.…”

Section: Modelingmentioning

confidence: 99%

Energetic mapping of oxide traps in MoS ₂ field-effect transistors

et al. 2017

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The performance of MoS 2 transistors is strongly affected by charge trapping in oxide traps with very broad distributions of time constants. These defects degrade the mobility and additionally lead to the hysteresis of the gate transfer characteristics, which presents a crucial performance and reliability issue for these new technologies. Here we perform a detailed study of the hysteresis in double-gated MoS 2 FETs and show that this issue is nothing else than a combination of threshold voltage shifts resulting from positive and negative bias-temperature instabilities. While these instabilities are well known from silicon devices, they are even more important in 2D devices given the considerably larger defect densities. Most importantly, the magnitudes of these threshold voltage shifts depend strongly on the density and energetic alignment of the active oxide traps. Based on this, we introduce the incremental hysteresis sweep method which allows for an accurate mapping of these defects and extract their energy distributions from simulations. By applying our method to analyze the impact of oxide traps situated in the Al 2 O 3 top gate of several devices, we confirm its versatility. Since all 2D devices investigated so far suffer from a similar hysteresis behavior, the incremental hysteresis sweep method provides a unique and powerful way for the detailed characterization of their defect bands.

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“…Note that we have ignored inelastic phenomena in the calculation of τ c such as electron-phonon coupling 20) and lattice relaxation. 21,22) It is because we aim to investigate the correlation of the CEV and z T in this work. A comprehensive study of capture and emission dynamics is another topic related to those inelastic physical phenomena that we may leave for future study.…”

Section: Simulation Samples and Methodologymentioning

confidence: 99%

Three-dimensional device simulation of random telegraph noise spectroscopy with Coulomb energy variation of the trap in high-k gate oxide

Lin

et al. 2018

Jpn. J. Appl. Phys.

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The random telegraph noise (RTN) time constants, capture (τc) and emission (τe) times, have been extensively used to identify the trap position in the gate oxide by comparing the measured τc-over-τe ratio with the Shockley–Read–Hall (SRH) statistics. However, various factors have been shown to affect the accuracy of the extracted trap depth from the SRH-type models, such as three-dimensional (3D) device electrostatics, atomistic doping, metal gate granularity, and Coulomb energy variation (CEV) of the trap. Focusing on CEV in this work, we assume the trap in gate oxide can be regarded as a floating island and then numerically studied the CEV of the trap with 3D drift-diffusion simulation. Analyzing the simulation data, the extracted trap depth without considering CEV in the SRH statistics are quantitatively compared with the data involved CEV.

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Advanced modeling of charge trapping: RTN, 1/f noise, SILC, and BTI

Cited by 16 publications

References 19 publications

On Border Traps in Back-Side-Illuminated CMOS Image Sensor Oxides

On Border Traps in Back-Side-Illuminated CMOS Image Sensor Oxides

Energetic mapping of oxide traps in MoS ₂ field-effect transistors

Three-dimensional device simulation of random telegraph noise spectroscopy with Coulomb energy variation of the trap in high-k gate oxide

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Advanced modeling of charge trapping: RTN, 1/f noise, SILC, and BTI

Cited by 16 publications

References 19 publications

On Border Traps in Back-Side-Illuminated CMOS Image Sensor Oxides

On Border Traps in Back-Side-Illuminated CMOS Image Sensor Oxides

Energetic mapping of oxide traps in MoS 2 field-effect transistors

Three-dimensional device simulation of random telegraph noise spectroscopy with Coulomb energy variation of the trap in high-k gate oxide

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Energetic mapping of oxide traps in MoS ₂ field-effect transistors