Advanced process modules and architectures for half-terahertz SiGe:C HBTs

Abstract

The European project DOTFIVE [1] addresses evolutionary scaling of self-aligned selective epitaxial base SiGe:C HBTs, investigates novel SiGe:C HBT architectures, and develops novel process modules to push SiGe BiCMOS towards 500 GHz F max and 2.5 ps gate delay. In this paper, scaling issues of SiGe:C HBT technology will be addressed. The limitations of the different commonly used architectures will be described, and measures taken in the project to overcome these limitations will be summarized. Initial results indicate that the objectives of the project can be reached.

245-GHz LNA, Mixer, and Subharmonic Receiver in SiGe Technology

“…Low-loss transmission lines could be designed with the two thick top-metal layers. and of the experimental transistors are reported to be 300 and 500 GHz, respectively [14].…”

Hydrodynamic device simulation of 200 GHz SiGe heterojunction bipolar transistors

“…In [14] equations (1), (2), and (3) are showed for silicon using the same value for all electron relaxation times. Since that the electron mobility and the electron impact ionization factor are functions of energy and momentum relaxation times [16], equations (2) and (3) It is possible to explain the base current performance when the energy and the mobility hydrodynamic relaxation times increase by the hole density current terms in the hydrodynamic model.…”

“…Several foundries have been offering SiGe HBTs with operating frequencies of 200 GHz and even beyond in BiCMOS technology, which are successfully being used for 32, 60 and 77 GHz circuits [2].…”

Automated model complexity reduction using the HICUM hierarchy

“…Also future mm-wave applications will very likely rely on the availability of such technologies (e.g. [2]). Furthermore, the complexity of these systems will increase, resulting in a larger number of transistors and, thus, higher simulation times during the design phase.…”