Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA

Banijamali, Bahareh; Ramalingam, Suresh; Nagarajan, K. V.; Chaware, Raghu

doi:10.1109/ectc.2011.5898527

Cited by 158 publications

(36 citation statements)

References 4 publications

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“…Recently, Multi-chip Modules (MCM) utilizing silicon interposer and Through-Silicon-Via (TSV) technologies have been used to fill the gap caused by the decreasing rate in Si node scaling and the ever increasing requirement on the integration of functionalities for Very Large Scale Integrated (VLSI) circuit devices [3]. This type of IC integration is often referred to as the 2.5 Dimensional (2.5D) IC integration since the chips are still packaged in a planar format on the interposer as seen in previous generations of MCM technologies.…”

Section: From Fcamp To 3d Sip With Tsvmentioning

confidence: 99%

Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration

Xue

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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The bandwidth for high performance networking switches and routers increases two to ten times in every new generation. This in turn drives the bandwidth requirements for the Application Specific Integrated Circuits (ASICs) and their external memory devices designed for the high performance network systems. 3D IC integration with its low power, high density and high bandwidth advantages is proposed to address the bandwidth challenges between the ASIC and its external memory. This paper presents a novel 3D IC architecture that includes a silicon interposer with Through-Silicon-Vias (TSV) and interconnect wiring layers on both sides of the silicon interposer. An ASIC chip measured at 22 mm x 18 mm x 0.4 mm is attached on top of the silicon interposer while two smaller memory chips with a size of 10 mm x 10 mm x 0.4 mm are attached to the bottom of the silicon interposer with micro-bump interconnections. A unique, double-sided Chip to Chip (C2C) joining process is developed to enable the ASIC and memory integration in true 3D System-in-Package (SiP) format. This 3D IC architecture will help to overcome the size limitation of the current silicon interposers due to the reticle size used in the lithographic wafer processing.The 3D IC stack is assembled on an organic package substrate with conventional solder bumps. Communications between the top ASIC die and the bottom memory dice are made through the TSVs and the wiring layers of the silicon interposer. Thermal and thermo-mechanical analysis of the 3D IC stack are used to evaluate the package thermal performance and for optimizing material selection and package reliability. Both the modeling and experimental characterization results are used to gain insights into the 3D IC technology for addressing the ASIC and memory bandwidth challenges and to develop the best practice for ASIC and memory integration for next generation high performance network systems.

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Section: From Fcamp To 3d Sip With Tsvmentioning

confidence: 99%

Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration

Xue

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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“…The warpage as well as reliability challenges 144 associated with building up the large size thin 2.5D TSI should be confronted as well.…”

Section: A 25d Tsi Technology Roadmapmentioning

confidence: 99%

Heterogeneous 2.5D integration on through silicon interposer

Zhang¹,

Lin²,

Wickramanayaka³

et al. 2015

Applied Physics Reviews

130

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“…Here, 3D thermo-mechanical finite element models were used to analyze global and local stresses [10]. Furthermore, 3D compact models were developed calculating electron and hole mobility change using piezoresistance coefficients of silicon [11][12].…”

Section: Tsv Keep-out-zone (Koz) Studymentioning

confidence: 99%

Outstanding and innovative reliability study of 3D TSV interposer and fine pitch solder micro-bumps

Banijamali

Ramalingam

Liu

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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Silicon interposer minimizes CTE mismatch between the chip and copper filled TSV interposer resulting in high reliability micro bumps. Furthermore, providing high wiring density interconnections and improved electrical performance are the reasons TSV interposer has emerged as a good solution and getting too much industry attention.Several DOEs and design/material optimizations were performed in order to yield high aspect ratio void-free TSV copper via and reliable micro-bumps. Quality and reliability of copper TSV and micro-bumps are monitored in-situ during the process. This paper presents the reliability results as well as micro-bump resistance data. In addition, pre-conditioning, EM, u-HAST, HTS and thermal-cycling measurements are presented to insure reliability of the design and the material selected for the 28nm technology TSV interposer FPGA.Furthermore, this paper details the outstanding TSV KeepOut-Zone study (KOZ) for an active silicon interposer and the effect of TSV stress on transistor electron and hole mobility. Finally, an advanced thermal study of TSV interposer technology is presented to cool down a high-performance 28nm logic die (thousands of micro-bumps) that is mounted on a large silicon interposer with Cu through silicon via. Several DOEs have been constructed to optimize thermal interface material selection, underfill material selection and to study the effect of high power and hot spots on underfill and solder bump material properties as well as the effect of bump pitch and underfill properties on the die junction temperatures. IntroductionAs the interconnect density is continuing to shrink, and the cost of fabricating finer pitch substrate is increasing, flip chip packaging with the conventional organic buildup substrate is facing a major challenge in fine pitch wiring. To address these needs, TSV interposer has emerged as a good solution [1][2][3]. TSV interposer provides high wiring density interconnection, minimizes CTE mismatch between the Cu/low-k die and the copper filled TSV interposer, and improves electrical performance due to shorter interconnection from the chip to the substrate.TSV interposer wafers are manufactured by etching vias through silicon wafers and filling the vias with metal. The two TSV methods commonly used in industry involve "viafirst/via-middle" and "via-last" process flows. The work in this paper uses the "via-first/via-middle" flow since it offers the greatest benefit of interconnect density.Typically, the TSV vias are etched using DRIE process to form a high aspect ratio via. The TSVs are typically 10-20 um in diameter and 50-100 um deep. The walls of the TSV are lined with SiO2 dielectric. Then, a diffusion barrier and a copper seed layer are formed. The via hole is filled with

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Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA

Cited by 158 publications

References 4 publications

Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration

Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration

Heterogeneous 2.5D integration on through silicon interposer

Outstanding and innovative reliability study of 3D TSV interposer and fine pitch solder micro-bumps

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