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Silicon interposer minimizes CTE mismatch between the chip and copper filled TSV interposer resulting in high reliability micro bumps. Furthermore, providing high wiring density interconnections and improved electrical performance are the reasons TSV interposer has emerged as a good solution and getting too much industry attention.Several DOEs and design/material optimizations were performed in order to yield high aspect ratio void-free TSV copper via and reliable micro-bumps. Quality and reliability of copper TSV and micro-bumps are monitored in-situ during the process. This paper presents the reliability results as well as micro-bump resistance data. In addition, pre-conditioning, EM, u-HAST, HTS and thermal-cycling measurements are presented to insure reliability of the design and the material selected for the 28nm technology TSV interposer FPGA.Furthermore, this paper details the outstanding TSV KeepOut-Zone study (KOZ) for an active silicon interposer and the effect of TSV stress on transistor electron and hole mobility. Finally, an advanced thermal study of TSV interposer technology is presented to cool down a high-performance 28nm logic die (thousands of micro-bumps) that is mounted on a large silicon interposer with Cu through silicon via. Several DOEs have been constructed to optimize thermal interface material selection, underfill material selection and to study the effect of high power and hot spots on underfill and solder bump material properties as well as the effect of bump pitch and underfill properties on the die junction temperatures. IntroductionAs the interconnect density is continuing to shrink, and the cost of fabricating finer pitch substrate is increasing, flip chip packaging with the conventional organic buildup substrate is facing a major challenge in fine pitch wiring. To address these needs, TSV interposer has emerged as a good solution [1][2][3]. TSV interposer provides high wiring density interconnection, minimizes CTE mismatch between the Cu/low-k die and the copper filled TSV interposer, and improves electrical performance due to shorter interconnection from the chip to the substrate.TSV interposer wafers are manufactured by etching vias through silicon wafers and filling the vias with metal. The two TSV methods commonly used in industry involve "viafirst/via-middle" and "via-last" process flows. The work in this paper uses the "via-first/via-middle" flow since it offers the greatest benefit of interconnect density.Typically, the TSV vias are etched using DRIE process to form a high aspect ratio via. The TSVs are typically 10-20 um in diameter and 50-100 um deep. The walls of the TSV are lined with SiO2 dielectric. Then, a diffusion barrier and a copper seed layer are formed. The via hole is filled with

This paper describes the industry's first heterogeneous Stacked Silicon Interconnect (SSI) FPGA family (3D integration). Each device is housed in a low-temperature cofired ceramic (LTCC) package for optimal signal integrity. Inside the package, a heterogeneous IC stack delivers up to 2.78Tb/s transceiver bandwidth. The resulting bandwidth is approximately three times that achievable in a monolithic solution. Mounted on a passive silicon interposer with through-silicon vias (TSVs), the heterogeneous IC stack comprises FPGA ICs with 13.1-Gb/s transceivers and dedicated analog ICs with 28-Gb/s transceivers. Optimization took place concurrently on multiple facets of the design which were necessary to successfully implement the 3-D integration. In particular, this paper outlines the choices that were made in terms of package substrate material and interposer resistivity in order to optimize 28Gb/s system channel characteristics. These choices were validated through extensive electrical simulation and test chip correlation. In addition, this paper describes the design and timing verification of inter-die interconnects, an area that the electronic design automation industry had not yet fully addressed. This paper further describes 3D thermal-mechanical modeling and analysis for package reliability. The modeling was performed to address package coplanarity issues and stresses imposed by the interposer on the active dice, the low-k dielectric material, the micro-bumps and the C4 attach. The results indicate heterogeneous stacked-silicon (3D) integration is a reliable method to build very high-bandwidth multi-chip devices that exceed current monolithic capabilities.

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SUMMARYQuite effective low-order finite element and finite volume methods for incompressible fluid flows have been established and are widely used. However, higher-order finite element methods that are stable, have high accuracy and are computationally efficient are still sought. Such discretization schemes could be particularly useful to establish error estimates in numerical solutions of fluid flows. The objective of this paper is to report on a study in which the cubic interpolated polynomial (CIP) method is embedded into 4-node and 9-node finite element discretizations of 2D flows in order to stabilize the convective terms. To illustrate the capabilities of the formulations, the results obtained in the solution of the driven flow square cavity problem are given.