Advanced TFT SRAM cell technology using a phase-shift lithography

Yamanaka, Toshiaki; Hashimoto, Takayuki; Hasegawa, Norio; Tanaka, Takeshi; Hashimoto, Norikazu; Shimizu, Akihiro; Ohki, N.; Ishibashi, Koji; Sasaki, K.; Nishida, Takashi; Mine, T.; Takeda, Eiji; Nagano, Takahiro

doi:10.1109/16.391213

Cited by 33 publications

(12 citation statements)

References 15 publications

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“…Of these, the increase of packing density using vertical integration of devices is particularly interesting, as it offers the additional benefits of decreasing block-level routing complexity (through the ability to layer blocks) and dramatically decreasing the consumed silicon realestate. Various simple vertically integrated cells have been demonstrated in the past, such as vertically integrated SRAM cells [3].…”

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confidence: 99%

High-performance germanium-seeded laterally crystallized TFTs for vertical device integration

Subramanian

Saraswat

1998

IEEE Trans. Electron Devices

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Abstract-Increasing chip complexity and area has resulted in interconnect delay becoming a significant fraction of overall chip delay. Continued scaling of design rules will further aggravate this problem. Vertical integration of devices will enable a substantial reduction in chip size and thus in interconnect delay. We present a novel technique to achieve vertical integration of CMOS devices. Germanium is used as a seeding agent at the source and/or drain of thin film transistors (TFT's) to laterally crystallize amorphous silicon films, resulting in high-performance devices. This is achieved through the formation of large grain polysilicon with a precise control over the location of the grain. TFT's have been demonstrated offering substantial performance improvement over conventional unseeded polycrystalline TFT's, with demonstrated mobilities as high as 300 cm 2 /V-s. The process is fully CMOS compatible and has a low thermal budget. It is highly scalable to deep-submicron technologies and, with suitable optimization, should enable the production of high-performance, high density, vertically integrated ULSI.

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confidence: 99%

High-performance germanium-seeded laterally crystallized TFTs for vertical device integration

Subramanian

Saraswat

1998

IEEE Trans. Electron Devices

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“…The GBFET, with its ideal characteristics is a perfect candidate in many applications such as active matrix liquid crystal displays (AMLCDs), random access memories, read only memories, linear image sensors, thermal printer heads and photodetector amplifiers [12][13][14][15].…”

Section: Discussionmentioning

confidence: 99%

Gate-induced barrier field effect transistor (GBFET) - a new thin film transistor for active matrix liquid crystal display systems

Kumar

Orouji

2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

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“…Polysilicon thin-film transistors (poly-Si TFTs) have attracted much considerable attention because of their wide application in active matrix liquid-crystal-displays (AMLCD), memory devices such as dynamic random access memories (DRAMs) [1], static random access memories (SRAMs) [2], and electrically erasable programmable read-only memories (EEPROMs) [3]. Especially, the application in AMLCDs is the primary trend, leading to the rapid development of poly-Si TFT technology.…”

Section: Introductionmentioning

confidence: 99%

Characteristics of poly-Si TFT combined with nonvolatile SONOS memory and nanowire channels structure

Chen

Chang

Liu

et al. 2007

Surface and Coatings Technology

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Advanced TFT SRAM cell technology using a phase-shift lithography

Cited by 33 publications

References 15 publications

High-performance germanium-seeded laterally crystallized TFTs for vertical device integration

High-performance germanium-seeded laterally crystallized TFTs for vertical device integration

Gate-induced barrier field effect transistor (GBFET) - a new thin film transistor for active matrix liquid crystal display systems

Characteristics of poly-Si TFT combined with nonvolatile SONOS memory and nanowire channels structure

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