Characteristics of poly-Si TFT combined with nonvolatile SONOS memory and nanowire channels structure

During thin film transistor (TFT) operation, gate dielectric is under a bias stress condition. In this work, bias stress effect for CdS TFT using HfO2 as gate dielectric is analyzed. Threshold voltage, Ion/Ioff ratio, and subthreshold slope were studied in order to understand changes produced at the dielectric semiconductor interface. We observed that threshold voltage shift is related with negative charge trapping in the dielectric/semiconductor interface and for this phenomenon we propose a trapping charge model. Finally, the TFT output characteristic was modeled considering a shift in the threshold voltage for each gate voltage curve.

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Characteristics of poly-Si TFT combined with nonvolatile SONOS memory and nanowire channels structure

Cited by 2 publications

References 10 publications

Effects of e-beam deposited gate dielectric layers with atmospheric pressure plasma treatment for IGZO thin-film transistors

Effects of e-beam deposited gate dielectric layers with atmospheric pressure plasma treatment for IGZO thin-film transistors

Electrical stress in CdS thin film transistors using HfO2 gate dielectric

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