Advanced wafer thinning technology and feasibility test for 3D integration

Kim, Young Suk; Maeda, Noritoshi; Kitada, Hideki; Fujimoto, Koji; Kodama, S.; Kawai, Akihito; Arai, K.; Suzuki, Kenkichi; Nakamura, Tomoji; Ohba, Takayuki

doi:10.1016/j.mee.2012.10.025

Cited by 76 publications

(33 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…among the commonly-used bonding adhesives like SU-8 (Iliescu et al 2006), polyimide (Bayrashev andZiaie 2003), and photoresist (Su et al 2001), benzocyclobutene (BcB) has emerging as a widely-used bonding adhesive in the applications of three-dimensional (3-D) integration (Kwon et al 2008;Zhang et al 2006;Kim et al 2013;Ohba et al 2010;lu et al 2003) and MeMS/microsensors (Dragoi et al 2008;Seok et al 2012;Zhou et al 2009;McMahon et al 2008). In MeMS/microsensor applications, BcB has been used as a permanent or temporary bonding material for wafer transfer or heterogeneous integration of MeMS/microsensors and integrated circuits (Brault et al 2010;lapisa et al 2011).…”

Section: Introductionmentioning

confidence: 99%

Void-free BCB adhesive wafer bonding with high alignment accuracy

et al. 2014

View full text Add to dashboard Cite

Section: Introductionmentioning

confidence: 99%

Void-free BCB adhesive wafer bonding with high alignment accuracy

et al. 2014

View full text Add to dashboard Cite

“…screen charge | atomic force microscopy | piezoresponse | charge scraping F erroelectric and piezoelectric materials have attracted great attention due to their applications in commercial markets such as a medical imaging (1-3), next generation inkjet printer heads (4), precision-positioning stages (5,6), fuel injectors in diesel engines (7,8), and memory devices (9,10). The macroscopic properties of ferroelectric and piezoelectric materials that make them appealing for current and future technologies can be more fully understood and improved through detailed knowledge of their domain structures at the nanoscale and mesoscale (11)(12)(13)(14)(15).…”

mentioning

confidence: 99%

Charge gradient microscopy

Hong

Tong

Park

et al. 2014

Proc. Natl. Acad. Sci. U.S.A.

View full text Add to dashboard Cite

Here we present a simple and fast method to reliably image polarization charges using charge gradient microscopy (CGM). We collected the current from the grounded CGM probe while scanning a periodically poled lithium niobate single crystal and single-crystal LiTaO 3 thin film on the Cr electrode. We observed current signals at the domains and domain walls originating from the displacement current and the relocation or removal of surface charges, which enabled us to visualize the ferroelectric domains at a scan frequency above 78 Hz over 10 μm. We envision that CGM can be used in high-speed ferroelectric domain imaging and piezoelectric energyharvesting devices.screen charge | atomic force microscopy | piezoresponse | charge scraping

show abstract

“…7 shows a schematic diagram of the grinding process. The wafer thickness uniformity after grinding was determined by the contact angle between the wheel and wafer surface [18]. The wafer was very slightly bowed after bonding due to deformation at the wafer edge where temporary adhesive was applied, and this uniformity was also reflected in the contact angle.…”

Section: Thinning and Device Characteristicsmentioning

confidence: 99%

Review of wafer-level three-dimensional integration (3DI) using bumpless interconnects for tera-scale generation

Ohba

Kim

Mizushima

et al. 2015

IEICE Electron. Express

Self Cite

View full text Add to dashboard Cite

The prospects of three-dimensional (3D) integration for Terabyte large scale integration using bumpless interconnects with low-aspect-ratio TSVs and ultra-thinning are discussed. Bumpless (no bump) interconnects between wafers are a second-generation alternative to the use of microbumps for Wafer-on-Wafer (WOW) technology. Ultra-thinning of wafers down to 4 µm provides the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of ThroughSilicon-Vias (TSVs). Our bumpless interconnects technology is classified into Via-Last, which is performed from the front side after thinning, and stacking Back-to-Front, in which any number of thinned 300 mm wafers and/or heterogeneous dies can be integrated. From an economic point of view, in many situations WOW is the leading 3D process because stacking at the wafer level drastically increases the processing throughput, and using multi-level bumpless interconnects, with individual wiring die-to-die, provides an appropriate yield that is equivalent to or greater than that achievable with 2D processes when scaling down to 22 nm nodes and beyond.

show abstract

Advanced wafer thinning technology and feasibility test for 3D integration

Cited by 76 publications

References 7 publications

Void-free BCB adhesive wafer bonding with high alignment accuracy

Void-free BCB adhesive wafer bonding with high alignment accuracy

Charge gradient microscopy

Review of wafer-level three-dimensional integration (3DI) using bumpless interconnects for tera-scale generation

Contact Info

Product

Resources

About