Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications

Dhar, Subhra; Pattanaik, Manisha; Rajaram, P.

doi:10.1155/2011/178516

Cited by 21 publications

(10 citation statements)

References 33 publications

(56 reference statements)

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“…A basic strategy to show SCE,threshold voltage move off in nanoscale n-channel FDSOI MOSFETs is exhibited. [3,4]The decrease of limit voltage with littler door length is a generally realized short channel impact named the "edge voltage move off" has been mimicked. By utilizing edge voltage(Vth), current-voltage bend have been distinguished for different working locales of MOSFETs with different channel lengths and furthermore for numerous oxide thickness.…”

Section: Methodology Of Threshold Modeling ( V Th )mentioning

confidence: 99%

Impact of Threshold Voltage roll off in Ultra Thin Fully Depleted Silicon on Insulator MOSFET

Tyagi,

Sharma,

Mani

2020

IJEAT

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This article is discussing about threshold voltage roll off effect in Ultra Thin Fully Depleted Silicon on Insulator MOSFET. The device performance is improved due to the reduction in threshold voltage roll off. The thickness of oxide layer is optimized to 2nm which also have a vital role in improvement of device’s throughput. The effect of oxide thickness on parasitic parameter also discussed. Device conductance and transconductance also take in account on simulating the ultra thin fully depleted SOIMOSFET

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Section: Methodology Of Threshold Modeling ( V Th )mentioning

confidence: 99%

Impact of Threshold Voltage roll off in Ultra Thin Fully Depleted Silicon on Insulator MOSFET

Tyagi,

Sharma,

Mani

2020

IJEAT

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“…With the continued miniaturization of the silicon CMOS transistor technology results in exponential increase in the efficiency of recent microprocessors for both single-core and multicore [1]. However, with the exponentially growing in number of transistors will increase the total number of required power and energy consumption per watt for today's high-performance microprocessors [2,3]. Now, at the system level architecture, energy efficiency is the central concept of high-performance microprocessor technology as well as the standard of transistors in the energy-efficient nanoelectronics era.…”

Section: Introductionmentioning

confidence: 99%

Analysis of ONOFIC Technique Using SiGe Heterojunction Double Gate Vertical TFET for Low Power Applications

Singh

Raj

2020

Silicon

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In this paper, a new technique ONOFIC is proposed and implemented for designing the SiGe heterojunction 2D double gate Vertical t-shaped TFET as an inverter circuit for low power applications. Initially, simulation done for both P-type and N-type of Vertical tTFET with same attributes using Sentaurus TCAD simulation tool. Thereafter, mixed mode technique is employed to understand the inverter circuit simulation's electrical characteristics and circuit efficiency. The workfucntion used for n-type Vertical TFET is 4.5 eV and for p-type Vertical TFET is 5.6 eV respectively. A 2D analytical model also implemented to capture the affecting parameters of leakage current and depletion length of the proposed model. Moreover, a new block technique named ONOFIC is inserted between the pull-up network and pull-down network of the circuit to regulator the trade-off between the power dissipation and reduced device dimensions. The method offers an excellent agreement between the propagation delay and power dissipation for designing efficient logic circuit. This article compares the efficiency of logic circuit like NAND, NOR and inverter circuit by estimating the power-delay product (PDP) with the conventional logic designs. The performance result show that the proposed model significantly reduces the leakage current for low power circuit applications.

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“…Device miniaturization increases the device density on single silicon bu®er and reduces the propagation delay of the logic block. 1 According to Moore, the number of devices that can be implemented on an integrated circuit doubles after every 18 months. 2 Further reduction in the size of the transistors face a lot of restrictions in ultra deep submicron regime.…”

Section: Introductionmentioning

confidence: 99%

“…Equation (1) shows that the threshold voltage of the device must be reduced proportionally by reducing the supply voltage of the device so that it should maintain the performance of the device. However, the main component of the leakage current called subthreshold, increases exponentially when the threshold voltage of the device is reduced.…”

Section: Introductionmentioning

confidence: 99%

Techniques for Low Leakage Nanoscale Vlsi Circuits: A Comparative Study

Sharma

Pattanaik

2014

J CIRCUIT SYST COMP

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Since the last two decades, the trend of device miniaturization has increased to get better performance with a smaller area of the logic functions. In deep submicron regime, the demand of fabrication of nanoscale Complementary metal oxide semiconductor (CMOS) VLSI circuits has increased due to evaluation of modern successful portable systems. Leakage power dissipation and reliability issues are major concerns in deep submicron regime for VLSI chip designers. Power supply voltage has been scaled down to maintain the performance yield in future deep submicron regime. The threshold voltage is the critical parameter to trade-o® the performance yield and leakage power dissipation in nanoscaled devices. Low threshold voltage improves the device characteristics with large leakage power in nanoscaled devices. Several leakage reduction techniques at di®erent levels are used to mitigate the leakage power dissipation. Lower leakage power increases the reliability by reducing the cooling cost of the portable systems. In this article, we are presenting the explanatory general review of the commonly used leakage reduction techniques at circuit level. We have analyzed the NAND3 gate using HSPICE EDA tool for leakage power dissipation at di®erent technology nodes in active as well as standby modes. Process, voltage and temperature e®ects are checked for reliability purpose. Our comparative results and discussion of di®erent leakage reduction techniques are very useful to illustrate the e®ective technique in active and standby modes.

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Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications

Cited by 21 publications

References 33 publications

Impact of Threshold Voltage roll off in Ultra Thin Fully Depleted Silicon on Insulator MOSFET

Impact of Threshold Voltage roll off in Ultra Thin Fully Depleted Silicon on Insulator MOSFET

Analysis of ONOFIC Technique Using SiGe Heterojunction Double Gate Vertical TFET for Low Power Applications

Techniques for Low Leakage Nanoscale Vlsi Circuits: A Comparative Study

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