Techniques for Low Leakage Nanoscale Vlsi Circuits: A Comparative Study

Sharma, Vibha; Pattanaik, Manisha

doi:10.1142/s0218126614500613

Cited by 21 publications

(4 citation statements)

References 25 publications

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“…where V TH0 is the zero-body-bias threshold voltage, V BS is the body bias, 2ϕ S is the surface voltage, K1 and K2 are the 1st-and 2nd-order body-bias coefficients, respectively, and Δ is a small change due to any device parameter type. The threshold voltage is a key parameter at the transistor-level design for controlling large leakage power [9]. Thus, several researchers have proposed numerous techniques by considering the variation in threshold voltage.…”

Section: Introductionmentioning

confidence: 99%

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A novel approach for designing of variability aware low‐power logic gates

Sharma

2022

ETRI Journal

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Metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short‐channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large‐scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor‐level input‐controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low‐power ICS approach is extensively discussed to verify its importance in low‐power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low‐power and high‐speed techniques at a 22‐nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5‐inverters.

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Section: Introductionmentioning

confidence: 99%

“…The threshold voltage is a key parameter at the transistor‐level design for controlling large leakage power [9]. Thus, several researchers have proposed numerous techniques by considering the variation in threshold voltage.…”

Section: Introductionmentioning

confidence: 99%

A novel approach for designing of variability aware low‐power logic gates

Sharma

2022

ETRI Journal

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“…In DSM regime, parameter variations of the devices also greatly a®ect the leakage power in several ways. 1 ICs have the most demanded impressive revolution in the¯eld of semiconductor industry. Today's microprocessors have large number of transistors on single chip and are clocked at giga hertz (GHz) clock speeds.…”

Section: Introductionmentioning

confidence: 99%

Design of Low Leakage Variability Aware ONOFIC CMOS Standard Cell Library

Sharma

Pattanaik

2016

J CIRCUIT SYST COMP

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In this research paper, a minimum set of low leakage variability aware ONOFIC CMOS digital standard cell library is developed. The developed standard cell library contains basic cells such as inverter, NAND, NOR, AND, OR and bu®er logic cells and characterized at 32 nm bulk CMOS process technology. All cells are designed, at 32 nm technology node under TT process corner at room temperature with power supply of 0.8 V by using Silvaco's EDA tools. All generated cells have same cell height of 1.58 m. The proposed logic cells attain large leakage and power delay product (PDP) reduction. ISCAS'85 benchmark circuits 74181 and c17 are designed and veri¯ed with developed logic cells at transistor level. The ONOFIC standard cell library reduces 34.40% and 42.74% leakage power and improves PDP by 18.34% and 16.46% for 74181 and c17 circuits, respectively. The result of generated standard cell library shows that it is a good choice for low leakage applications.

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“…The leakage of a two transistor stack is about an order of magnitude less than the leakage in a single transistor. Mechanism like input dependence increases the number of off transistor in a stack of transistor by properly choosing the input of gates and thereby reduces the standby leakage current [9].…”

Section: Introductionmentioning

confidence: 99%

A Low Leakage Input Dependent ONOFIC Approach for CMOS Logic Circuits

2016

6th International Conference on Advances in Engineering Sciences and Applied Mathematics (ICAESAM-2016) Dec. 21-22, 2016 Kuala

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With the rise of the number of electronic portable devices, the importance of leakage power reduction techniques are increasing. Leakage power dissipation has become one of the critical issues in modern integrated circuit. This work focuses on the low power circuit design, which is showing an ever increasing growth with the scaling of technology nodes. Supply voltage and threshold voltage of the device are scaled down to maintain the performance at lower technology nodes. Reduction in threshold voltage causes leakage power in the concerned device. The number of gates per chip has been increasing with technology scaling which resulted in large leakage power dissipation. The demand of low power integrated circuits is increasing to improve the performance of portable systems. In this research paper, a low leakage circuit level approach is proposed in order to overcome the leakage power dissipation. 4:1 multiplexer is designed and simulated at 32nm technology node by using proposed approach and the results are compared with the conventional 4:1 multiplexer circuit.

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Techniques for Low Leakage Nanoscale Vlsi Circuits: A Comparative Study

Cited by 21 publications

References 25 publications

A novel approach for designing of variability aware low‐power logic gates

A novel approach for designing of variability aware low‐power logic gates

Design of Low Leakage Variability Aware ONOFIC CMOS Standard Cell Library

A Low Leakage Input Dependent ONOFIC Approach for CMOS Logic Circuits

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