Advantages of the Graded-Channel SOI FD MOSFET for Application as a Quasi-Linear Resistor

Silicon on Insulator Technology Review

“…• More functions [63,32] per die area or reduced die area per function; SOI [110,99] allows tighter layout design rules (higher integration density), mainly due to reduced STI layout area required for lateral junction isolation (resulting from the absence of wells and the possibility of direct contact of the source-drain diodes in the NMOS and PMOS transistors)…”

Analysis of uniaxial and biaxial strain impact on the linearity of fully depleted SOI nMOSFETs

“…In this configura- tion, the device source/drain regions are used as resistor terminals and the gate voltage is tuned for a certain onresistance (R ON ). Generally long-channel transistors are used to obtain high R ON [23,24]. The study of the linearity properties has been performed in devices with W = L = 1 lm at V GT = 800 mV sweeping V DS in the range À1 V 6 V DS 6 1 V, representing a dynamic variation of 2 V peak-to-peak.…”

“…No differences between HD3 of biaxially strained SOI or combined uniaxially and biaxially strained films can be identified. Typically, for filters HD3 specifications smaller than À60 dB are required [23]. Thus, using the experimental data of Fig.…”

Harmonic distortion of 2-MOS structures for MOSFET-C filters implemented with n-type unstrained and strained FINFETS

“…Active RC filters such as the MOSFET-C are good candidates when low power is required, since they allow for the use of fully-depleted SOI devices, improving the power consumption even in deep sub-micron technologies [4][5][6]. In these filters, MOS transistors working in the linear regime are applied as tunable resistors [7]. The drain and the source of the transistor play the role of the resistor terminals and the gate voltage (V GS ) controls the resistance.…”