AES Encryption Algorithm Hardware Implementation: Throughput and Area Comparison of 128, 192 and 256-bits Key

Adib, Samir El; Raissouni, Naoufal

doi:10.11591/ijres.v1i2.551

Cited by 6 publications

(3 citation statements)

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“…AES algorithm can be implemented using different methods and contributions which can be categorized as follows. In the first one, loop unrolling and iterative techniques are used to increase throughput to area ratio and decrease area cost [12,13]. The second category includes the designs which use pipelining and full-pipelining techniques to increase operational frequency and throughput [6], [14].…”

Section: Previous Workmentioning

confidence: 99%

High throughput FPGA Implementation of Advanced Encryption Standard Algorithm

Oukili

Bri

2017

TELKOMNIKA

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The growth of computer systems and electronic communications and transactions has meant that the need for effective security and reliability of data communication, processing and storage is more important than ever. In this context, cryptography is a high priority research area in engineering. The Advanced Encryption Standard (AES) is a symmetric-key criptographic algorithm for protecting sensitive information and is one of the most widely secure and used algorithm today. High-throughput, low power and compactness have always been topic of interest for implementing this type of algorithm. In this paper, we are interested on the development of high throughput architecture and implementation of AES algorithm, using the least amount of hardware possible. We have adopted a pipeline approach in order to reduce the critical path and achieve competitive performances in terms of throughput and efficiency. This approach is effectively tested on the AES S-Box substitution. The latter is a complex transformation and the key point to improve architecture performances. Considering the high delay and hardware required for this transformation, we proposed 7-stage pipelined S-box by using composite field in order to deal with the critical path and the occupied area resources. In addition, efficient AES key expansion architecture suitable for our proposed pipelined AES is presented. The implementation had been successfully done on Virtex-5 XC5VLX85 and Virtex-6 XC6VLX75T Field Programmable Gate Array (FPGA) devices using Xilinx ISE v14.7. Our AES design achieved a data encryption rate of 108.69 Gbps and used only 6361 slices ressource. Compared to the best previous work, this implementation improves data throughput by 5.6% and reduces the used slices to 77.69%.

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Section: Previous Workmentioning

confidence: 99%

High throughput FPGA Implementation of Advanced Encryption Standard Algorithm

Oukili

Bri

2017

TELKOMNIKA

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“…Advanced Encryption Standard (AES) is one of most frequently used symmetric algorithms because of its combination of security, performance both in hardware and software, efficiency, and flexibility [3]. AES was established by National Institute of Standards and Technology (NIST) to replace DES [4] and 3DES and with a key length of 128, 192, and 256 bits. It takes a 128-bit data length and considers it as an array of bytes, and takes it as a 4x4 matrix called states.…”

Section: Introductionmentioning

confidence: 99%

Modified AES for Text and Image Encryption

Gamido

Sison

Medina

2018

IJEECS

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Advanced Encryption Standard (AES) is one of the most frequently used encryption algorithms. In the study, the Advanced Encryption Standard is modified to address its high computational requirement due to the complex mathematical operations in MixColumns Transformation making the encryption process slow. The modified AES used Bit Permutation to replace the MixColumns Transformation in AES since bit permutation is easy to implement and it does not have any complex mathematical computation. Results of the study show that the modified AES algorithm exhibited increased efficiency due to the faster encryption time and reduced CPU usage. The modified AES algorithm also yielded higher avalanche effect which improved the performance of the algorithm.

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“…Indeed, described in RFC3711 (reference document), the SRTP protocol is the security solution of the transport protocol of the voice data which is the most used in practice. So, the SRTP uses the AES (Advanced Encryption Standard) algorithm ( [6], [9], [13], [16], [18], [24]) for encryption; the HMAC-SHA-1 (Hash message authentication code -Secure Hash Algorithm 1) algorithm [26] for authentication and the Diffie Hellman (DH) protocol for key exchange [2]. However, this protocol still has several shortcomings, in particular: the key exchange problem imposed by AES, the non-repudiation service which is not well-guaranteed due to the certification system which isn't used, and in addition, this protocol is not suitable for multi-point communications [28].…”

Section: Introductionmentioning

confidence: 99%