Affordable and effective screening of delay defects in ASICs using the inline resistance fault model

Benware, B.; Lu, Cheng-Tse; Slyke, J. Van; Krishnamurthy, P.; Madge, R.; Keim, Martin; Kassab, Mark; Rajski, J.

doi:10.1109/test.2004.1387403

Cited by 26 publications

(11 citation statements)

References 14 publications

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“…In cases where no SA like behavior is reported, the steady state prediction may be useful in detecting the open. A transition fault test [33] like the one applied for resistive defects is also helpful in this case since no transition is propagated through the defective line.…”

Section: A Short Linesmentioning

confidence: 99%

Gate Leakage Impact on Full Open Defects in Interconnect Lines

Arumí

Rodríguez-Montañés

Figueras

et al. 2011

IEEE Trans. VLSI Syst.

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Section: A Short Linesmentioning

confidence: 99%

Gate Leakage Impact on Full Open Defects in Interconnect Lines

Arumí

Rodríguez-Montañés

Figueras

et al. 2011

IEEE Trans. VLSI Syst.

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“…Based on the above discussion, a simple and straightforward approach for generating IRF tests using an existing ATPG tool for TDF was proposed in [13]. In this paper we adopt the same method for generating IRF tests.…”

Section: Relationship Between Irf and Tdf Fault Modelmentioning

confidence: 99%

“…However a TDF test set can contain unnecessary test patterns for proper screening of this type of defect. Recently the inline resistance fault (IRF) model [13] was proposed to model the resistive interconnect open defects. In this fault model it is assumed that both the rising and the falling transitions at a circuit node are delayed if the node is faulty, and hence it is sufficient to test only one of the slow-to-rise or the slow-to-fall transition fault at a node in the circuit to detect the corresponding inline resistance fault.…”

Section: Introductionmentioning

confidence: 99%

“…It was shown that test sets obtained for the IRF model are considerably smaller than the TDF test sets while providing the same coverage of finite resistance interconnect open defects. The second type of open defects which are detected by two-pattern tests are intra-gate opens, which are modeled by TSOP faults. In recent years several studies [13,14,15] have revealed that a considerable number of defective chips exhibit sequence dependent but timing independent (SDTI) failures. Such failures can be symptomatic of intra-gate opens of infinite resistance (TSOP faults).…”

Section: Introductionmentioning

confidence: 99%

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Test Generation for Open Defects in CMOS Circuits

Devta-Prasanna

Gunda²,

Krishnamurthy³

et al. 2006

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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Open defects in CMOS circuits require two-pattern tests for detection. Traditionally, the only two-pattern tests included in manufacturing test are those targeting transition delay faults. Such tests, however, do not provide complete coverage of all the open defects. In this paper we propose the use of a unified test set that detects all inline resistance faults which model interconnect open defects and all transistor stuck-open faults which model intra-gate open defects in order to obtain a comprehensive coverage of open defects. We also describe a method of generating the proposed test set using an ATPG program for transition delay faults whose sizes are comparable to transition delay fault based test set.

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“…Current-based testing techniques are often used to complement the coverage of such faults [Benw04]. Interestingly, using our bridging fault simulator [Hari03] reveals that bridging fault coverage of more than 99% was reachable for our CUT examples, with a TDF test set provided by a commercial tool.…”

Section: • Applying Moderately Fast Functional Test Patternsmentioning

confidence: 99%