AFRA: A low cost high performance reliable routing for 3D mesh NoCs

Akbari, Morteza; Shafiee,; Fathy,; Berangi,

doi:10.1109/date.2012.6176490

Cited by 39 publications

(16 citation statements)

References 14 publications

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“…Akbari et al proposed AFRA [15], a simple and low overhead routing that can tolerate just vertical faulty links. This scheme relies on ZXY and XZXY routings in absence and presence of faulty links respectively.…”

Section: Related Workmentioning

confidence: 99%

A low overhead, fault tolerant and congestion aware routing algorithm for 3D mesh-based Network-on-Chips

Jouybari

Mohammadi

2014

Microprocessors and Microsystems

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Section: Related Workmentioning

confidence: 99%

A low overhead, fault tolerant and congestion aware routing algorithm for 3D mesh-based Network-on-Chips

Jouybari

Mohammadi

2014

Microprocessors and Microsystems

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“…The link uses M+N wires to support at mos links require the circuits to distribute bit in order to extract the N original bits [14] In many other researches, fault pro with routing algorithms. AFRA [15] presented for the 3D mesh network. simple routing ZXY and XZXY in presence of faults, respectively.…”

Section: Related Wormentioning

confidence: 99%

Fault-tolerant circular routing algorithm for 3D-NoC

Alizadeh

Saneei

Ebrahimi

2014

2014 International Congress on Technology, Communication and Knowledge (ICTCK)

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ExpandingNetworks-on-Chip (NoCs) to the third dimension (3D-NoC) has been known as a promising solution for the latency challenges of future many-core Systems-on-Chip. 3D-NoC may take advantages of TSVsfor vertical links which are shorter and faster than horizontal ones. Faults may occur in TSVs as well as the horizontal links though faults inTSVs are more costly. In this paper, we present a fault-tolerant routing algorithm targeting faults in both TSVs and horizontal links. The proposed routing algorithm is based on defining some circular routing paths which offers a deadlock-free routing for packets in meshbased topologies. In addition to tolerating faults, these circular pathshelp in reducing congestion in the centralpart of the network at high injection rates. The proposed circular routing algorithm is able to tolerate all one-faulty links. In addition, it is shown that its performance is better than those of traditional methods.

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“…Such works dealt with this challenge by suggesting redundant TSV links [19], reliable routings [48]- [51], error detection/correction HW modules [52], or TSV-variationaware synthesis [53]. One approach for reliable routings, which is suitable for both 2-D and 3-D NoC interconnection network, is leveraging reconfigurable routing table to keep fault-tolerant routing paths [48], [49].…”

Section: Related Workmentioning

confidence: 99%

“…This method is highly resilient but suffers from poor scalability due to the area required for the tables. The other approach is applying ZXY routing, but dynamically determining when a packet moves vertically, so that incoming packets never use the faulty TSVs [50], [51]. Those are, therefore, designed to tackle faults on vertical links since fault rate on TSVs is much larger than conventional horizontal ones (i.e., metal wire).…”

Section: Related Workmentioning

confidence: 99%

Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory

Kang

Benini

Micheli

2015

IEEE Trans. VLSI Syst.

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Abstract-3-D integrated circuits (3-D ICs) offer a promising solution to overcome the scaling limitations of 2-D ICs. However, using too many through-silicon-vias (TSVs) pose a negative impact on 3-D ICs due to the large overhead of TSV (e.g., large footprint and low yield). In this paper, we propose a new TSV sharing method for a circuit-switched 3-D mesh-of-tree (MoT) interconnect, which supports high-throughput and lowlatency communication between processing cores and 3-D stacked multibanked L2 scratchpad memory. The proposed method supports traffic balancing and TSV-failure tolerant routing. The proposed method advocates a modular design strategy to allow stacking multiple identical memory dies without the need for different masks for dies at different levels in the memory stack. We also investigate various parameters of 3-D memory stacking (e.g., fabrication technology, TSV bonding technique, number of memory tiers, and TSV sharing scheme) that affect interconnect latency, system performance, and fabrication cost. Compared to conventional MoT interconnect [6] that is straightforwardly adapted to 3-D integration, the proposed method yields up to ×2.11 and ×1.11 improvements in terms of cost efficiency (i.e., performance/cost) for microbump TSV bonding and direct Cu-Cu TSV bonding techniques, respectively. Index Terms-3-D integration, multicore, networks-on-chip (NoC), scratchpad memory (SPM).

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AFRA: A low cost high performance reliable routing for 3D mesh NoCs

Cited by 39 publications

References 14 publications

A low overhead, fault tolerant and congestion aware routing algorithm for 3D mesh-based Network-on-Chips

A low overhead, fault tolerant and congestion aware routing algorithm for 3D mesh-based Network-on-Chips

Fault-tolerant circular routing algorithm for 3D-NoC

Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory

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