Algorithm and FPGA implementation of interpolation‐based soft output MMSE MIMO detector for 3GPP LTE

This paper studies the design requirements and challenges of SDR (Software-Defined Radio) vector processors for 5G micro base stations. Pareto principle reflects the rule of "vital few and trivial many", which states that 80% of consequences stem from 20% of causes. Since 20% of the instructions account for about 80% of the running time of the micro base station processor, it is essential to speed up the 20% instructions as the complex vector operations consuming most of the runtime. This paper proposes instruction fusion strategy and black-box acceleration strategy to speed up the kernel function of the micro base station algorithms. The experimental results show that the instruction fusion strategy can make the performance improvement ratio reach up to 17% while running the BDTI/ EEMBC benchmark, and the black-box acceleration strategy can make the performance improvement ratio reach about 5% while running the kernel of matrix inversion. In addition, our SIMD micro architecture is designed as a vector processor to eliminate the extra costs when implementing kernel micro scheduling. This paper provides a reference for the hardware implementation of 5G micro base stations with low cost and low-power consumption.

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“…Paper [10] modify the Banachiewicz formula for matrix inversion to avoid division operation. In the same way, B −1 can be written as follows…”

Section: ) Matrix Acceleration Instructionmentioning

confidence: 99%

Design Space Exploration of SDR Vector Processor for 5G Micro Base Stations

Chen¹,

Liu

Bai

et al. 2021

IEEE Access

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“…The task of a soft-output detector is to compute the soft value indicating reliability in the shape of log-likelihood ratio (LLR) for each code bit. We apply the low-complexity linear MMSE detector [18] to firstly compute the Gram matrix G n = H H n H n and the inverse of the regularized Gram matrix V n = (G n + σ 2 I Nt ) −1 for each subcarrier. Then, we compute the MMSE filter outputs as…”

Section: System Model and Soft-output Mmse Detectormentioning

confidence: 99%

“…To reduce the number of base points, [17] proposed a Gaussian approximation based phase shifted interpolation method for matrix inversion, which approximately estimates the required number of base points for each real-time implementation thereby reducing the complexity further. [18] proposed a Banachiewicz formula based matrix inversion algorithm with low complexity. But all these interpolation based algorithms were designed for small-size MIMO and cannot be easily extended to massive MIMO-OFDM applications.…”

Section: Introductionmentioning

confidence: 99%

A low cost interpolation based detection algorithm for medium-size massive MIMO-OFDM systems

Fang

Huang

et al. 2017

2017 17th International Symposium on Communications and Information Technologies (ISCIT)

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Abstract-The great potential of exploiting millimeter wave (mmwave) frequency spectrum for emerging fifth-generation (5G) wireless networks has motivated the study of massive multipleinput multiple-output (MIMO) for achieving high data rate. For medium-size massive MIMO with orthogonal frequency division multiplexing (OFDM) uplink systems, the minimum mean square error (MMSE) based soft-output detector is often used due to its better bit error rate (BER) performance compared to the matched filter detector. Although the multipath channel can be converted into a set of parallel flat-fading channels by using OFDM thus reducing the complexity of receiver design, the tone by tone (per subcarrier) detection methods based on the state-of-the-art low complexity MMSE still incur considerably high computational complexity since the number of tones is typically very large. To reduce the complexity, the interpolationbased matrix inversion algorithms for small-size MIMO-OFDM systems have been proposed, which compute the matrix inversion by interpolating separately the adjoint and determinant. In this paper, we find that the (regularized) Gram matrix inversions have strong correlation between different subcarriers. By exploiting this strong correlation, we propose a linear interpolation based MMSE detection algorithm that directly interpolates the inverted MMSE matrices for a small number of subcarriers to obtain matrix inversions for all other subcarriers, thereby significantly reducing the number of matrix inversion required. Extensive simulations show that with small BER performance loss compared to the exact MMSE detector, the proposed algorithm can reduce the complexity to the level of the matched filter algorithm.

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“…Field-programmable gate-array (FPGA) devices are widely used for implementation of multiuser and MIMO detectors [Salari et al, 2014;Barbero and Thompson, 2006;Yang et al, 2013;Quan et al, 2015]. Existing hardware designs mostly deal with small-size systems.…”

Section: Introductionmentioning

confidence: 99%

“…To meet these demands, it is expected that future communication systems, i.e., beyond 4G or 5G systems, will reach a faster data rate at gigabit‐scale over the next few years. The conventional small‐size multiple‐input multiple‐output (MIMO) detectors have been proposed in the literature [ Rao et al , ; Tadza et al , ; Salari et al , ; Cong et al , ]. All these architectures require matrix inversion.…”

Section: Introductionmentioning

confidence: 99%

FPGA design of box‐constrained DCD‐based detector for large‐scale MIMO systems

Quan

Zakharov

2016

Radio Science

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This paper proposes an improved architecture of a low‐complexity box‐constrained multiple‐input multiple‐output (MIMO) detector which is based on the dichotomous coordinate descent (DCD) algorithm. This architecture allows a simple field‐programmable gate‐array implementation of the detector and explores the parallel implementation to reduce the number of clock cycles required in the design. We investigate the proposed design and compare its detection performance, hardware resources, and convergence speed with that of known designs. It is shown that the proposed design provides improvement in the detection performance compared to the minimum mean square error (MMSE) detector. The numerical results also show that the proposed architecture requires as few as 184, 210, and 223 slices for 16 × 16, 64 × 64, and 128 × 128 MIMO systems, respectively, which is significantly less than that required by known designs of the MMSE detector. By comparing the serial and parallel implementations of the box‐constrained detector, we show that the parallel implementation requires 15% fewer clock cycles.

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Algorithm and FPGA implementation of interpolation‐based soft output MMSE MIMO detector for 3GPP LTE

Cited by 10 publications

References 22 publications

Design Space Exploration of SDR Vector Processor for 5G Micro Base Stations

Design Space Exploration of SDR Vector Processor for 5G Micro Base Stations

A low cost interpolation based detection algorithm for medium-size massive MIMO-OFDM systems

FPGA design of box‐constrained DCD‐based detector for large‐scale MIMO systems

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