Algorithmic Factorisation forLlow Power FPGA Implementations Through Increased Data Locality

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

“…Power savings of between 36 and 37% that is, from 1616 to 1029 mW, were achieved over the Xilinx and Amphion designs with even higher savings against the other core [9]. Area savings were also made with the design as it used only 35% of the slices and 50% of the DSP48E blocks when compared to the Xilinx design and 20% of the slices when viewed against the Amphion design which does not use any DSP48E blocks.…”

“…described in detail in [9] with the intention here to use the results to demonstrate the usefulness of the technique. The approach (QFFT) was coded in VHDL, synthesised using the Xilinx-II FPGA technology and then implemented on the Xilinx XUP Virtex-II Pro board which has been specifically created to allow power measurements to be taken.…”

“…Area savings were also made with the design as it used only 35% of the slices and 50% of the DSP48E blocks when compared to the Xilinx design and 20% of the slices when viewed against the Amphion design which does not use any DSP48E blocks. These area gains should be treated lightly as it is not clear what additional functionality either of the two comparative designs had; however, based on the post place and route analysis, there is clear indication that the QFFT design results in much smaller interconnect; more detail on this work is given in [9]. The availability of the Virtex-II XUP board allowed actual measurements to be made.…”

“…It is well known that increasing this data locality has a direct relationship to the power consumed [5 -7]. Indeed, previous work has involved investigating locality properties for FPGA-based systolic array implementations [8] and an FFT-based digital receiver solution based on a Xilinx Virtex-II FPGA implementation [9]; however, the real challenge is how to influence data locality at the algorithmic level in a systematic fashion, particularly for fast transforms that may not necessarily exhibit this locality in the first instance.…”

Power efficient dynamic-range utilisation for DSP on FPGA

“…The full dynamic-range is partitioned into separable processing threads allowing several data streams to be computed concurrently resulting in an architecture that requires 51-56% less power than existing cores with no loss of precision. This work builds upon and works in harmony with an existing high level low power methodology for DSP cores [5] [6].…”