Power efficient DSP datapath configuration methodology for FPGA

McKeown, S.; Woods, Roger; McAllister, John

doi:10.1109/fpl.2008.4629997

Cited by 2 publications

(6 citation statements)

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“…The data locality factorisation process results in architectures consisting of repetitive, power efficient processing clusters, within which a synergy exists with the 'datapath configuration' strand [6]; here commonality in mutually exclusive operations of variable-length DSP algorithms is exploited to achieve increased operational capacity. Commonality in core computational operations of algorithmic variations is identified and mapped to a static architecture of processing elements, with a flexible routing structure to implement the required functionality.…”

Section: Power Efficient Methodologymentioning

confidence: 99%

“…Commonality in core computational operations of algorithmic variations is identified and mapped to a static architecture of processing elements, with a flexible routing structure to implement the required functionality. Leveraging locally interconnected processing clusters arising out of the data locality technique as the basis of the static architecture allows this to be achieved in an extremely power efficient manner [6].…”

Section: Power Efficient Methodologymentioning

confidence: 99%

“…The intersection between algorithms is analysed in tabular format ([h]) and a single DFG (dataflow graph) produced matching union of the combined resource requirements. For the 16/256-point FFT example, this process results in an architecture with a 100% increase in operational capacity in 16-point mode but which requires 19% less peak power, 33% fewer multipliers and 12% fewer slices [6] than using existing cores.…”

Section: Fig 32 16-point Matrix Factorised and Index Mappedmentioning

confidence: 97%

“…This has been described in depth in [6], but parts relevant to this paper are highlighted here in additional detail. In EW, it is critical to entirely capture a pulse envelope in a high resolution digital representation during the initial ADC stage.…”

Section: Application Domainmentioning

confidence: 98%

“…The full dynamic-range is partitioned into separable processing threads allowing several data streams to be computed concurrently resulting in an architecture that requires 51-56% less power than existing cores with no loss of precision. This work builds upon and works in harmony with an existing high level low power methodology for DSP cores [5] [6].…”

Section: Introductionmentioning

confidence: 98%

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Power efficient dynamic-range utilisation for DSP on FPGA

McKeown¹,

Woods²,

McAllister³

2008

2008 IEEE Workshop on Signal Processing Systems

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A power and resource efficient 'dynamic-range utilisation' technique to increase operational capacity of DSP IP cores by exploiting redundancy in the data representation of sampled analogue input data, is presented. By cleverly partitioning dynamic-range into separable processing threads, several data streams are computed concurrently on the same hardware. Unlike existing techniques which act solely to reduce power consumption due to sign extension, here the dynamic range is exploited to increase operational capacity while still achieving reduced power consumption. This extends an existing system-level, power efficient framework for the design of low power DSP IP cores, which when applied to the design of an FFT IP core in a digital receiver system gives an architecture requiring 50% fewer multipliers, 12% fewer slices and 51%-56% less power.

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Section: Power Efficient Methodologymentioning

confidence: 99%

Section: Power Efficient Methodologymentioning

confidence: 99%

Section: Fig 32 16-point Matrix Factorised and Index Mappedmentioning

confidence: 97%

Section: Application Domainmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 98%

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Power efficient dynamic-range utilisation for DSP on FPGA

McKeown¹,

Woods²,

McAllister³

2008

2008 IEEE Workshop on Signal Processing Systems

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Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA

Chen

Akella

2011

ACM Trans. Reconfigurable Technol. Syst.

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We explore the use of Data-Level Parallelism (DLP) as a way of improving the energy efficiency and power consumption involved in running applications on an FPGA. We show that static power consumption is a significant fraction of the overall power consumption in an FPGA and that it does not change significantly even as the area required by an architecture increases, because of the dominance of interconnect in an FPGA. We show that the degree of DLP can be used in conjunction with frequency scaling to reduce the overall power consumption. ACM Reference Format:Chen, X. and Akella, V. 2011. Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on a FPGA.

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Power efficient DSP datapath configuration methodology for FPGA

Cited by 2 publications

References 10 publications

Power efficient dynamic-range utilisation for DSP on FPGA

Power efficient dynamic-range utilisation for DSP on FPGA

Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA

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